JPH10341150A - Current generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current generating circuit that generates an injection current to supply to an IIL circuit with high accuracy. SOLUTION: In a current generating circuit that generates an injection current I12 feed to an IIL circuit 20, a reference current I11 generated from a current source 11 based on an externally mounted resistor is reflected by a current mirror circuit 12 and a resulting injjection current I12 is fed to the IIL circuit 20, and a dummy circuit 23 of the same circuit configuration as that of the current mirror circuit 12 is provided to a reference current side of the current mirror circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current generation circuit, and more particularly to a current generation circuit for generating an injection current supplied to an IIL (Integrated Injection Logic) circuit.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional circuit of this kind. In the figure, a reference current I is provided between a power supply Vcc and a ground.
A current source 101 for flowing 101 is connected to, for example, three diodes 102 to 104 serially connected in a forward direction. The base of the transistor 105 is connected to a connection point A between the current source 101 and the anode of the diode 102. The collector of the transistor 105 is connected to the power supply Vcc.

A resistor 107 is connected between the emitter of the transistor 105 and the current supply terminal 106a of the IIL circuit 106.
Is connected. The IIL circuit 106 includes a p-type transistor having an emitter connected to the current supply terminal 106a and a base grounded.
np transistor 108 and this pnp transistor 1
08 and an npn transistor 109 whose base is connected to the input terminal 106b, whose collector is connected to the output terminal 106c, and whose emitter is grounded.

[0004]

In the conventional circuit having the above structure, when the forward voltage of the diode and the emitter-base voltage of the bipolar transistor are Vf, the reference current I101 of the current source 101 causes three points at the connection point A.
A voltage of Vf is generated. Thereby, the IIL circuit 106
The injection current I102 supplied to the
If the resistance value of 07 is R0, it is determined by the following equation.

As is apparent from the equation (1), the variation in the forward voltage Vf of the diode and the variation in the absolute value of the resistance value R0 directly cause the variation of the injection current I102. There is a problem that it cannot be obtained well. In the worst case, the operation of the IIL circuit 106 becomes unstable due to the influence of the injection current I102.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a current generating circuit capable of accurately generating an injection current to be supplied to an IIL circuit. .

[0007]

SUMMARY OF THE INVENTION A current generating circuit according to the present invention generates a current source for supplying a reference current based on an external resistor, and generates an injection current corresponding to the reference current of the current source and supplies it to an IIL circuit. The current mirror circuit includes a dummy circuit including a transistor having an emitter and a base connected between a reference current side and a reference potential point of the current mirror circuit.

In the current generating circuit having the above configuration, a stable reference current is generated by using an external resistor in the current source. The current mirror circuit generates an injection current by folding the reference current, and supplies the injection current to the IIL circuit. At this time, if the emitter-base voltage of the bipolar transistor is Vf, the current supply terminal of the IIL circuit is
A voltage of f is generated. On the other hand, the same voltage Vf is also generated at the current supply terminal of the dummy circuit. Therefore, the voltage of Vf is canceled.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, a current source 11 is connected to a power supply Vcc, and the current source 11 generates a stable predetermined reference current I11 using an external resistor. A specific circuit example of the current source 11 will be described later. The reference current I11 of the current source 11 is turned back by the current mirror circuit 12 to become an injection current I12.

The current mirror circuit 12 includes npn transistors 13 and 14 whose bases are connected in common, resistors 15 and 16 each having one end connected to each emitter of the transistors 13 and 14, and transistors 13 and 14. Diode 1 with anode connected to connected base
7 and a resistor 1 having one end connected to the cathode of the diode 17 and the other end connected to the ground which is a reference potential point.
8, a base is connected to the collector of the transistor 13, and the emitter is connected to the base.
and an npn transistor 19 connected to cc.

In the current mirror circuit 12, the transistors 13 and 14 have substantially the same characteristics. Also, resistors 15 and 16 having the same resistance value are used. Diode 17, resistor 18
The transistor 19 is provided to obtain an injection current I12 having substantially the same current value as the reference current I11.

The resistor 16 on the side of the injection current I12
The IIL circuit 20 has a current supply terminal 20a
Connected at The IIL circuit 20 includes a pn circuit having an emitter connected to the current supply terminal 20a and a base grounded.
The pnp transistor 21 has a one-stage gate configuration including an npn transistor 22 having a collector connected to the input terminal 20b, a collector connected to the output terminal 20c, and an emitter grounded, together with the collector of the pnp transistor 21.

The IIL circuit 20 is a logic circuit having the advantages of low power consumption and high integration.
The current supply terminal 20a of the IIL circuit 20 is connected to the reference current I11 of the current source 11 by the current mirror circuit 12.
, An injection current I12 having a current value substantially the same as the reference current I11 in the present embodiment.

A dummy circuit 23 having the same circuit configuration as the IIL circuit 20, for example, is connected to the other end of the resistor 15 on the side of the reference current I11 via a current supply terminal 23a. That is, the dummy circuit 23 includes an pnp transistor 24 having an emitter connected to the current supply terminal 23a and a grounded base, and an pnp transistor 24 having a base connected to the collector of the pnp transistor 24 and having an emitter grounded.
and an n-transistor 25.

FIG. 2 shows an example of a specific circuit configuration of the current source 11. In the figure, a DC power supply 27 for generating a voltage Vr without variation is connected between an inverting (-) input terminal of an operational amplifier 26 and a power supply Vcc. The output terminal of the operational amplifier 26 has an npn transistor 2
8 and 29 are connected. The emitters of these transistors 28 and 29 are grounded via resistors 30 and 31. The collector of the transistor 28 is connected to the non-inverting (+) input terminal of the operational amplifier 26 and to the power supply terminal 32. An external resistor 33 is connected between the power supply terminal 32 and the power supply Vcc.

In this current source 11, the voltage at point A is
Since the feedback is applied by the operational amplifier 26, the voltage is always Vcc-Vr. Therefore, assuming that the resistance value of the external resistor 33 is R21, the current I0 flowing through the collector of the transistor 28 is I0 = Vr / R21, and is a stable current without variation. The same applies to the current I1 flowing through the collector of the transistor 29.
This current I1 becomes the reference current I11 in FIG.

In the current generating circuit according to an embodiment of the present invention, the emitter-base voltage of the bipolar transistor is Vf, and the resistances of the resistors 15 and 16 are R11 and R11.
12, the emitter potential V11 of the transistor 13
Is R11 × I11 + Vf. The emitter potential V12 of the transistor 14 is the same as that of the conventional circuit, that is, R12 × I12 + Vf.

Here, since V11 = V12,
The injection current I12 is as follows: I12 = (R11 × I11 + Vf−Vf) / r12 = (R11 / R12) · I11 (2)

As is apparent from the equation (2), the dummy circuit 23 having the same circuit configuration as the IIL circuit 20 is added to the other end of the resistor 15 on the reference current I11 side.
Emitter-base voltage Vf of bipolar transistor
It can be seen that the variation is canceled. Also, I
In C, since the characteristics of the pair of resistors manufactured in the same chip are excellent, the resistance values R1 of the resistors 15 and 16 are different.
Variations in the absolute values of 1 and R12 can also be suppressed.

In the present embodiment, the dummy circuit 23 having the same circuit configuration as the IIL circuit 20 is added to the other end of the resistor 15 on the reference current I11 side. However, the present invention is not limited to this. In the case of a dummy circuit including a transistor having an emitter and a base connected between the other end of the reference 15 and the ground which is a reference potential point, as is apparent from the equation (2), the variation of the emitter-base voltage Vf varies. Can be canceled.

However, the dummy circuit 23 is connected to the IIL circuit 20
It is preferable that the circuit configuration be completely the same as that of the reference current I11 of the current mirror circuit 12 and the injection current I12.
Since the symmetry with the side can be increased, this is advantageous in circuit configuration.

FIG. 4 is a circuit diagram showing another embodiment of the present invention applied to an IIL circuit having n (n is an integer of 2 or more) gate stages. In FIG. 4, a current source 51 is connected to a power supply Vcc, and the current source 51 generates a stable predetermined reference current I21 using an external resistor. As the current source 121, one having a circuit configuration shown in FIG. 2 is used. The reference current I21 of the current source 51 is
It is turned back by the current mirror circuit 52 to become an injection current I22.

The current mirror circuit 22 includes npn transistors 53 and 54 whose bases are connected in common, resistors 55 and 56 each having one end connected to each emitter of the transistors 53 and 54, and transistors 53 and 54. Diode 5 with anode connected to connected base
7, a resistor 58 having one end connected to the cathode of the diode 57 and the other end connected to the ground, a base connected to the collector of the transistor 53, an emitter connected to the base, and a collector connected to the power supply Vcc. and an npn transistor 59.

In the current mirror circuit 52, the transistor 54 is a multi-emitter transistor having n (n is an integer of 2 or more) emitters. Accordingly, the resistance values R21 and R22 of the resistors 55 and 56 are
It is set so that n × R21 = R22.

The resistor 66 on the side of the injection current I22
The IIL circuit 60 has a current supply terminal 60a
Connected at The IIL circuit 60 includes n pnp transistors 61-1 to 61-n whose emitters are commonly connected to the current supply terminal 20a and whose bases are grounded, and the bases of the transistors 61-1 to 61-n. N npn transistors 62-1 to 62-n each connected to each collector, each collector is connected to each collector of transistors 61-2 to 61-n in the next stage, and each emitter is grounded. And a six-stage gate configuration.

The first stage npn transistor 62-1
Is connected to the input terminal 60b, and the final stage npn
The collector of the transistor 62-n is connected to the output terminal 60c. In the IIL circuit 60, an injection current I22 (= n × I11) that is n times the reference current I21 of the current source 151 is supplied to the current supply terminal 60a by the current mirror circuit 52. At this time, I
The reference current I21 flows through each gate in the IL circuit 60.

The other end of the resistor 55 on the reference current I21 side is connected to a dummy circuit 63 having a circuit configuration for one gate of the IIL circuit 60 at a current supply terminal 63a. That is, the dummy circuit 63 includes an pnp transistor 64 having an emitter connected to the current supply terminal 63a and a grounded base, and an pnp transistor 64 having a base connected to the collector of the pnp transistor 64 and an emitter grounded.
and an n-transistor 65.

In the current generating circuit according to another embodiment of the present invention, assuming that the emitter-base voltage of the bipolar transistor is Vf, the voltage V11 generated at the current supply terminal 63a of the dummy circuit 63 and the current supply of the IIL circuit 60 The voltage V22 generated at the terminal 60a becomes Vf, and the Vf of the IIL circuit 60 can be canceled. That is, in the current generating circuit that supplies the injection current I22 to the IIL circuit 60 including the n-stage gates, the dummy circuit 63 having a circuit configuration for one gate of the IIL circuit 60 is added to the reference current I21 side. Vf variation can be canceled.

Further, even if the number of gates of the IIL circuit 60 is n, the emitter size S
21, S22 is S2: S22 = 1: n, and the resistance 55, S22
The resistance values R21 and R22 of 56 are R21: R22 = n: 1.
Since the characteristics of the pair of circuit elements manufactured in the same chip in the IC are excellent, the variation in the resistance values R21 and R22 of the resistors 55 and 56 can be suppressed. The injection current I22 which is n times the reference current I21 can be obtained with high accuracy.

In this embodiment, as in the previous embodiment, instead of the dummy circuit 63 having a circuit configuration of one gate, the other end of the resistor 55 and the ground which is the reference potential point are connected. By adding a dummy circuit including a transistor to which an emitter and a base are connected between them, a variation in the emitter-base voltage Vf can be canceled.

In each of the above embodiments, a dedicated dummy circuit is provided on the reference current side. However, as shown in FIG. 4, the IIL circuit 60 can be used also as a dummy circuit. In this case, since the voltage V21 completely matches the voltage V22, there is an advantage that the variation in Vf can be surely canceled and the circuit configuration can be simplified by omitting the dummy circuit.

As described above, in a circuit configuration in which the IIL circuit 60 is also used as a dummy circuit, when n≫1,
Since the injection current I22 is extremely large with respect to the reference current I21, even if the current of (I21 + I22) flows into the IIL circuit 60 as the injection current, the ratio occupied by the reference current I21 is extremely small, and each gate has the reference current I21. Therefore, there is no practical problem since a current almost equal to the current flows.

However, when n> 1, the reference current I2
Since the ratio occupied by 1 increases, it is necessary to set the number of gate stages of the IIL circuit 60 to n + 1. Thus, when applied to the IIL circuit 60 with n> 1, the IIL circuit 60
Even if the circuit 60 is also used as a dummy circuit, there is no problem because the reference current I21 flows through each gate.

[0035]

As described above, according to the present invention,
The reference current generated by the external resistor is turned back by the current mirror circuit and supplied as an injection current to the IIL circuit, and the emitter and the base are connected between the reference current side of the current mirror circuit and the reference potential point. By providing the dummy circuit including the transistor, the emitter-base voltage Vf of the bipolar transistor of the IIL circuit can be canceled, and since the characteristics of the circuit element manufactured in the same chip are excellent, the injection into the IIL circuit is performed. The current can be generated with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of a current source.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a modification of the present invention.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

11, 51: current source, 12, 52: current mirror circuit, 20, 60: IIL circuit, 23, 63: dummy circuit, 26: operational amplifier, I11, I21: reference current, I
12, I22 ... injection current

Continuation of the front page (72) Inventor Fumiya Tokudome 5-1 Noguchikita, Kokubu-shi, Kagoshima

Claims (3)

[Claims] 1. A current generating circuit for generating an injection current to be supplied to an IIL circuit, comprising: a current source for flowing a reference current based on an external resistor; and an injection current corresponding to the reference current of the current source. A current mirror circuit for supplying current to the IIL circuit; and a dummy circuit including a transistor having an emitter and a base connected between a reference current side of the current mirror circuit and a reference potential point. circuit. 2. The current generating circuit according to claim 1, wherein said dummy circuit has the same circuit configuration as said IIL circuit. 3. The current generating circuit according to claim 2, wherein said IIL circuit is also used as said dummy circuit.