JPS5826676B2 - light emitting diode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in visible light emitting diodes.
In particular, the present invention provides a light emitting diode with a pn junction formed in the lateral direction, which has low power consumption and high luminous efficiency.

Conventional visible light emitting diodes are made of GaAs using phosphor conversion.
and diodes such as GaAsPGaP which themselves emit visible light.

To light up these light emitting diodes, connect both ends of them.
It is necessary to apply a voltage of about 1 to 25V.

Now, when these light emitting diodes are to be used as a pilot lamp in a power supply circuit or as a numeric display driven by a transistor, the difference between the power supply voltage of the power supply or transistor and the voltage applied across the light emitting diode is replaced by a resistor, transistor, diode, The voltage is dropped by multiple light emitting diodes.

Particularly, it is very wasteful in terms of power consumption to drop most of the voltage difference using a resistor.

Conventionally, in order to improve this problem, a method has been adopted in which a plurality of light emitting diodes are connected in series and wired as shown in FIGS. 1a and 1b.

In FIG. 1a, the cathode 12 of the first light emitting diode 1 and the anode 21 of the second light emitting diode 2 are connected, and a voltage is applied between the anode 11 of the diode 1 and the cathode 22 of the diode 2. This shape becomes larger and the wiring becomes complicated.

On the other hand, the first solution is to assemble the tanzaku-shaped light emitting diodes 3 and 4, which are often used for numerical displays, in a hybrid manner, but the number of diodes and wirepons required is increased by the number of wires connected in series.

The present invention proposes a light emitting diode that improves these drawbacks.

The light emitting diode of the present invention provides a light emitting diode with low power consumption and high luminous efficiency by forming pn junctions in the lateral direction.

Furthermore, the light emitting diode of the present invention has high voltage resistance and can also emit light directly even with alternating current.

FIG. 2 shows the basic structure of the light emitting diode of the present invention, in which 5 is an n-layer single crystal semiconductor substrate, 6 is an i-layer or an n-layer epitaxially grown on the substrate 5, 71, 72°73.74 are the p layer, n layer, p
layer, n layer, 8 is an insulating layer, and 9 is a conductive layer.

When a positive terminal is connected to the conductive layer provided on the 9th layer 71 and a negative terminal is connected to the conductive layer provided on the n layer 74 and a forward bias is applied, the junction between the 9th layer 71 and the n layer 72 and the 9th layer 73 are connected. n
Light is emitted at the junction of layers 74.

This light emission is extracted from the regions of the nine layers 71 and 73 where no conductive layer is provided.

Note that the substrate 5 does not essentially have to be an n layer, and may be a p layer or an i layer.
However, an n-layer may be used, but an n-layer is used from the viewpoint of cost.

On the other hand, the epitaxial layer 6 is desirably formed of an i-layer, but even if the epitaxial layer 6 is an n-layer, if the current (2) flowing through the layer 6 is sufficiently larger than the current (2) flowing across the junction, light emission can be obtained at three p-n junctions.

The light emitting diode of the present invention will be explained in detail below using Examples.

[Example 1] FIG. 3 is a perspective view of a light emitting diode of this example, and FIG. 4 is a manufacturing process diagram of the diode shown in FIG. 3.

In FIGS. 3 and 4, 10 is a gallium phosphide substrate;
11 is an i-layer formed by epitaxial growth on the substrate 10, 12 is an n-type layer epitaxially grown on layer 11, and 12' is a ■-shaped groove dug in the n-type layer 12 by mesa etching. The depth is shallower than the thickness of the n-type layer 12.

13 is a p-type layer formed by diffusion in the groove 12' of the n-type layer 12, and the diffusion depth of the p-type layer is such that at least one p-type layer reaches layer 11 at the apex of the ■-shaped groove. Must be greater than or equal to depth.

14 is an insulating layer, 15 is an n-type ohmic electrode, and 16 is a p-type ohmic electrode.

This manufacturing method will be explained below in order of steps.

First, as shown in FIG. 4, a 111-plane gallium phosphide substrate 1
Prepare 0 and place 1 on the 111th surface of the substrate 10 as shown in ■.
The layer 11 is epitaxially grown, and further eight layers 12 are epitaxially grown on the first layer 11 as shown in (2).

Next, a striped etching mask 14 is provided on the eight layers 12 as shown in (3).

Note that the etching mask 14 has a 112 direction perpendicular to the 110 direction.
It is formed of a striped Au film or the like in the direction.

Next, as shown in (3), the eight layers 12 are etched with a phosphoric acid solution at 120°C.

The etching time is controlled so that the etching depth is shallower than the thickness of the eight layers 12.

The groove 12' dug by etching is as shown in ■■
Etched into glyphs.

Next, as shown in (■), Zn is etched through the etching mask 14.
is diffused to form nine layers 13 in the ■-shaped grooves 12'.

The depth of the p-layer must be greater than or equal to the depth at which the p-layer reaches at least one layer 11 at the apex of the ■-shaped groove.

In this way, eight layers 12 are divided by nine layers 13.

Next, as shown in ■, a part of the mask 14 is removed and the 8 layers 12 are removed.
expose a part of

Next, as shown in ■, the ohmic electrodes 15 and 9 of the 8 layers 12
An ohmic electrode 16 of layer 13 is provided.

Note that the n-layer ohmic electrode 15 is made of AuSn, AuSi
The p-layer ohmic electrode 16 was formed using A[.

Finally, as shown in (3), the light emitting diode is cut into units and lead wires 17 and 18 are attached to the ohmic electrodes 15 and 16, respectively.

When a forward bias is applied between the lead wires 17 and 18 of the light emitting diode obtained by the above method, light is emitted at the pn junction.

This light emission is reflected by the electrode 16 covering the nine layers 13 and taken out to the substrate 10 side.

Also, at this time, the angle of the apex of the ■-shaped groove dug in the p layer was 60
By selecting the etching conditions so that the etching conditions are close to .degree., the light emitted at the joint can be extracted more effectively.

In summary, the present invention involves epitaxially growing an n layer on a layer epitaxially grown on a 111-plane gallium phosphide surface, etching this n layer to dig a ■-shaped groove in the 112 direction perpendicular to the 110 direction, and A light-emitting diode in which a p-layer is formed in the groove by diffusion, the n-layer is divided into a p-layer and an i-layer, and a pnpn junction is formed laterally.This light-emitting diode has low power consumption, high luminous efficiency, and has an increased reverse breakdown voltage. can be obtained.

Although the present invention has shown an example of a pnpn junction in which two pn junctions are incorporated, the arrangement is not limited to two pn junctions.

[Brief explanation of the drawing]

Figures 1a and 1b show conventional light emitting diodes;
2 is a schematic configuration diagram, b is a perspective view, FIG. 2 a is a sectional view showing the basic configuration of the light emitting diode of the present invention, FIG.
The figure is a perspective view showing a specific structure of a light emitting diode according to an embodiment of the present invention, and FIG. 4 is a sectional view showing the manufacturing process of the light emitting diode shown in FIG. 3 in order. 10...Substrate, 11...i layer, 12.
...N-type layer, 13...P-type layer, 15...
...N-type ohmic electrode, 16...P-type ohmic electrode.

Claims (1)

[Claims] 1 has an i-layer on the 111 plane of a gallium phosphide substrate, has an n-layer having a ■-shaped groove in the 112 direction perpendicular to the 110 direction on the i-layer, and has the n-type groove portion 1. A light-emitting diode comprising a p-layer provided by diffusion into the diode, the n-layer being divided into a p-layer and an i-layer to form a pnpn junction in the lateral direction.