JPS5826454Y2 - denshisensou sagata shiryyoukansatsusouchi - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a scanning circuit in an electron beam scanning sample observation apparatus.

In a device such as a scanning electron microscope, an electron beam is used to scan the sample surface, and a cathode ray tube is also scanned at the same time to create an image of the sample surface, but it takes a considerable amount of time to complete scanning one screen.・So even if the fluorescent surface of the cathode ray tube is made of a material with afterglow properties, by the time the lower part of the screen is being scanned, the upper part of the image will be considerably faded.

To prevent this, you can increase the scanning speed, but
In this case, the frequency range of the video signal to maintain the same image quality expands to the higher side, so the frequency characteristics of the video circuit must be made to have a wide range. There is a limit to speed.

Therefore, in order to prevent blurring of the edges of the image without increasing the scanning speed, interlaced scanning is performed.

Normally, interlaced scanning includes horizontal scanning an integer plus 1/2 times within the retrace period of vertical scanning, so that the starting point of the first horizontal scanning is at the top edge and the top center of the screen every other time. I have to.

The present invention attempts to provide an interlaced scanning circuit that is completely different from such conventional interlaced scanning methods.

In this invention, by varying the upper limit level of the vertical scanning signal by an integer of the interval between two consecutive horizontal scanning lines for each scanning, the horizontal scanning lines in the first, second, etc. vertical scanning are overlapped. This was done to prevent this from happening.

FIG. 1A shows the waveform of the vertical scanning signal, and the range A is the scanning period, and the upper limit level of the signal is changed by d every scan.

Therefore, as shown in Figure 2, with respect to the horizontal scanning line (solid line) during the first vertical scanning, the horizontal scanning lines during the vertical scanning period of the two circuits enter the center of each of the first horizontal scanning lines. .

FIG. 3 shows a circuit for changing the upper limit level of the vertical scanning signal each time as shown in FIG. 1a.

In is a control signal input terminal, OUT is a vertical scanning signal output terminal, and a signal having the waveform shown in FIG. 1a is output.

Assuming that the output of amplifier IC2 is saturated on the negative side and the voltage at point 1 is -Vcc, transistor Q1 is conductive, and the potential at point 2 is also approximately -Vcc, and transistor Q2 is also conductive.

Therefore, the inverting terminal of ICI is negative, and the current flowing into terminal 7 flows toward Ql, and charging of the integrating capacitor C is stopped.

During this period, the voltage at the output terminal OUT is the voltage at point 5, which is the voltage at point 4 (base of Ql) + the pace-emitter voltage of Q2 (voltage at point 3), the Zener voltage of Zener diode D2, and the voltage inside diode D1. This gives the upper limit level of the waveform of FIG. 1a, which can be set appropriately by adjusting the potentiometer VR2 and changing the voltage at point 4.

Next, when a negative inversion pulse enters the terminal In, the voltage at one point is +V
cc, Ql is cut off, point 2 becomes +Vcc, Ql is also cut off, and capacitor C begins to be charged by the current flowing into terminal 7.

Since the amplifier C1 and the capacitor C constitute an integrating circuit, the voltage at the output point 5 of the IC1 decreases linearly over time.

This period is one vertical scanning period shown in FIG.
The inverted pulse (Fig. 1b) applied to the horizontal scanning start signal is a start signal for vertical scanning, and this inverted pulse is taken out at fixed intervals from the horizontal scanning start signal. and the first horizontal scan are started at the same time.

As the voltage at point 5 decreases, the voltage at point 6 also decreases to below the voltage at point 8, and the voltage at output point 1 of amplifier IC2 returns to -Vcc.

Therefore, the transistor Ql. Ql conducts and capacitor C
is discharged through Ql, the 5-point voltage rises, and the state returns to the initial state, that is, the state in which the OUT output is stopped at the upper limit level.

At this point, two white inversion pulses are applied to the In terminal.

In the above operation, FIG. 1 shows the inversion pulse entering the In terminal, and C shows the voltage change at point 1.

This changes in a rectangular waveform between +Vcc and -Vcc.

The lower limit level in Fig. 1a is the feedback resistance vR1 of the amplifier IC1.
It is variable by adjusting.

Since the output voltage at point 1 is changing as shown in Figure 1C, when trigger flip-flop F is triggered at the falling edge of this voltage, the output of F is inverted every vertical scan and becomes an output as shown in Figure 1D. issue.

By dividing this output voltage using resistors and applying voltages at nine points to the potentiometer VR2, the upper limit level of the vertical scanning signal can be raised or lowered by half the interval between two horizontal scanning lines for each vertical scan. .

FIG. 4 shows an embodiment in which one screen is completed by three or more interlaced scans, and in the circuit of FIG.

2. A signal of a constant level appears in sequence.

This signal is applied to amplifier IC3 via resistors R1, R2, etc.

Rf is a feedback resistor and the output of IC3 is Rf/R1, R1/R
2. It changes as follows.

This output voltage is applied to the potentiometer VR2 shown in FIG.

In this way, the scanning lines on the screen can be interlaced scanned in a manner such that second, third, etc. scanning lines are inserted between the first scanning line, as shown in FIG.

The interlaced scanning circuit of the present invention has the feature that interlaced scanning of any number of lines can be easily realized with the above-described configuration.

In other words, when performing interlaced scanning with multiple skips, the vertical scanning period is an integer multiple of the horizontal scanning period plus an arbitrary number, which is an odd relationship, and the vertical and horizontal scanning signals are a common multiple of the frequencies of both scanning signals. However, according to the present invention, the upper limit level of the vertical scanning signal is changed stepwise in synchronization with the vertical scanning. Since it is only
Interlaced scanning (including one-line skipping) can be easily realized by simply selecting and switching the voltage dividing resistor that determines the upper limit level using a counter.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram of the vertical scanning signal and its control signal in the present invention, Fig. 2 is a diagram showing scanning lines in interlaced scanning (in the case of single interlaced scanning), and Fig. 3 is an embodiment of the present invention. 4 is a circuit diagram of another embodiment, and FIG. 5 is a circuit diagram of another embodiment.
FIG. 6 is a diagram showing the state of scanning lines in interlaced scanning according to the illustrated embodiment; F...Flip-flop, K...Counter.

Claims (1)

[Scope of utility model registration request] In a vertical scanning signal generation circuit that generates a sawtooth wave by switching the charging and discharging of an integrating circuit that includes a capacitor and maintains the upper limit of the output constant, the horizontal The charging and discharging of the vertical scanning signal generating circuit is reversed by signals extracted at a certain number of intervals from the start signal of the scanning signal, and when it is detected that the output of the vertical scanning signal has become below a certain lower limit level, the circuit is activated again. In addition to reversing the charging and discharging, the upper limit level of the output of the vertical scanning signal generating circuit is set to two adjacent horizontal scanning signals by the output of an arbitrary numeric counter that advances the count every cycle of the circuit's operation. An electron beam scanning type specimen observation apparatus configured to stepwise switch the level difference of vertical scanning signals corresponding to the line spacing by - by the above-mentioned arbitrary number.