JPS5826272B2 - How to protect an inverter using a gate turn-off thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter protection method using a gate turn-off thyristor that can be turned off at the gate, and particularly relates to a method for protecting an inverter using a gate turn-off thyristor that can be turned off at the gate.
Alternatively, the present invention aims to provide an improved protection method that effectively suppresses the peak value, di/dt, etc., and prevents the gate turn-off thyristor from being destroyed.

In general, a gate turn-off thyristor (hereinafter abbreviated as GTO)
Since the arc-extinguishing circuit can be simplified, and furthermore, there is no need to pay much consideration to the commutation surface, and the 0N-OFF period can be set high, it is suitable for high-frequency inverters using pulse width modulation method. has various advantages such as being optimal, but on the other hand, in order to improve the blocking ability of the gate, the device itself must have a special structure, and the most important thing is that the forward voltage increase at turn-off Rate (d
v/dt), its peak value, and forward current increase rate (d
If the thyristor (i/dt) etc. are not suppressed within the specified rated values, the element itself will permanently break down and become inoperable, and these effects are much more serious than in ordinary thyristors.

First, FIG. 1 shows a typical circuit example of an inverter to which a GTO is applied.

In this circuit example, only one phase is illustrated, but the other phases are also constructed in the same manner as in FIG.

In the figure, Ed is a DC power source, and this DC power source may have a configuration in which a neutral point is drawn out.

Su and Sx are GTOs, and a reactor LutLx is inserted in series with the GTOs, and Du and Dx are commutation diodes.

1 and 2 are surge absorption circuits that absorb surges during dv/dt or commutation, and as shown in the figure, this circuit consists of a capacitor Cu, a resistor Ru, a diode du, and a capacitor Cx.
Each of them is composed of a resistor Rx and a diode dx.

Considering an example of a circuit configured in this manner, it is assumed that, for example, a circulating current is flowing through the diode Dx as indicated by the solid arrow.

When GTO8u is turned on under this condition, a short circuit of 5u-Dx is formed and a short circuit current flows through Su.

In order to suppress di/dt of this short circuit current, reactors Lu and Lx are inserted.

Next, consider the case where Su is turned on and the load current flows in the direction of the dotted arrow. Under this condition, it is assumed that an off-gate current is supplied to Su and it is turned off.

When Su is turned off, the current flowing through Su decreases as shown in Figure 2, and assuming that this short-term interstitial charge current is constant, L increases in order to compensate for the decrease in the Su current.
Current flows through each path of u-Cu-Ru and Lx-RxCx.

In this process, capacitors Cu and Cx are gradually charged, and the voltage between the terminals of Su is determined by the charging voltage of capacitor Cu, and the forward voltage increase rate (dv/
dt).

When this Cu charge voltage becomes equal to the DC voltage Ed, the diode Du becomes conductive, and the load current begins to flow through the diode Du.

The energy stored in the reactor Lu and the wiring actance is transferred to the capacitor Cu, and this energy causes the Cu voltage to rise to Ep, which is higher than the DC voltage Ed, as shown by the broken line in FIG.

In this way, in the conventional circuit example shown in Fig. 1, d i at turn-on
/dt is suppressed by reactor Lut Lx, and dv/dt at turn-off is suppressed by a surge absorption circuit, but the problem with this circuit example is the capacitance of the capacitor and resistor that make up the surge absorption circuit. How about the selection?

That is, considering the case where Su is turned on, the di/dt of the short circuit current is suppressed to the desired value by the reactor Lu as described above, but the electric charge charged in the capacitor Cu is discharged through Su.

Here, regarding the capacitance of capacitor Cu, dv/d
In order to suppress the peak value Ep of t or dv/dt, C
The larger the capacity of u, the better.

However, if the capacitance of Cu is increased, the power loss of Ru caused by the discharge current of Cu can be expressed as WRC=:CEd2f (where Ed is the DC power supply voltage value and f is the ON frequency of Su), so from this formula, As is clear, the larger the capacity of Cu, the greater the power loss and the lower the efficiency, which is not preferable.

Furthermore, the power loss is greatly affected by the ON frequency of Su, so if Cu is a dog, the discharge time constant of Cu-Ru becomes large.
Since the dv/dt due to the charge voltage during charging becomes a problem, the capacity of Cu cannot be made very large.

Next, regarding the capacity of the resistor Ru, if Ru is made smaller, the peak value ip of the discharge current flowing through Su becomes a dog as shown in Figure 3A, and the loss when ON also increases, which destroys Su. There are probably many.

Therefore, the capacitance of Ru cannot be made very small, and on the other hand, if Ru is made large, the discharge time constant of Cu-Ru becomes too small, which is not very desirable.

In other words, when Su is turned on, the electric charge charged in Cu is discharged through Su. Figures 3A and 3B show the relationship among the Cu charging voltage, discharge current, Su voltage, and load current during this discharge. FIG. 3B shows the relationship between the discharge time constant τ of Cu-Ru and the ON frequency of Su.

That is, each capacitance of Cu p Ru is large and the discharge time constant of Cu-Ru is τ, while the ON frequency (inverter frequency) of Su is smaller than the discharge time constant τ, and as shown in FIG. 3B, Su is OFF at time t1. It shall be.

If such a relationship exists, the electric charge charged to Cu cannot be fully discharged at the time t1 of <5uOOFF, as shown in FIG. 3B, and a state of 11 charges of a voltage of Eo occurs.

In this way, a current commensurate with the decrease in the current of the charge voltage Su at the initial value Eo will be newly charged through Lu (this phenomenon is shown in Figure 2), so the voltage of Cu will be as shown in Figure 4. As shown, the initial voltage value Eo increases over time, and the voltage increase rate dv/dt of this charge voltage is low, and at the same time, the switching loss is large, so it poses a great threat to Su.

As described above, in the circuit shown in Figure 1, no matter how you choose the capacitance of the capacitor and resistor in the surge absorption circuit, contradictory results will result, and effective dv/dt suppression and suppression of its peak value will not be possible. It is possible.

The present invention was developed in view of this point, and will be described in detail below based on each embodiment shown in FIG.

First, before describing this embodiment, what should be done about the relationship between the CR discharge time constant τ of the surge absorption circuit and the inverter frequency f?
How to perform the most effective dv/dt will be specifically explained.

According to the present invention, the peak value E of dv/dt at turn-off
The first feature is that p is suppressed by a newly provided protection circuit, and the second feature is that only the off-time dv/dt is suppressed by the surge absorption circuit of the conventional circuit example.

That is, in order to reduce the switching loss and the C-R discharge time constant, the capacitor should have as small a capacity as possible, and the suppression resistor should also be used.

Therefore, in the present invention, since the dv/dt at turn-off is absorbed only by the surge absorption circuit, the C-R discharge time constant τ of the surge absorption circuit is set as follows with respect to the inverter frequency f. By determining this, dv/dt can be effectively suppressed.

That is, "-CR<f" The embodiment shown in FIG. 5 shows a specific circuit diagram for suppressing the peak value of dv/dt at turn-off by taking such a relational expression into consideration. Components that are the same as in Figure 1 are labeled with the same symbols and buttons.As is clear from the figure, the feature of this embodiment is that a diode D0 is connected in parallel to the positive side reactor Lu of the U arm, and the X arm Diodes are connected in parallel to the positive and negative reactors of each arm, such as diode D2 is connected in parallel to the negative reactor Lx of the arm. , the peak value of dv/dt at turn-off is suppressed.

That is, it is assumed that in the embodiment shown in FIG. 5, a load current is flowing through the element Su of the U arm, and the element Su is turned off by a predetermined OFF gate signal.

When the element Su is turned off in this way, as detailed in the circuit of FIG. 1, a charging current flows to the capacitor Cu of the first surge absorption circuit through the reactor Lu to compensate for the decrease in the current of the element Su. This charging voltage increases at a curve indicated by a broken line in FIG.

When the charging voltage reaches the DC power supply voltage Ed, the load current returns through the flywheel diode Du, and the energy stored in the reactor Lu and wiring inductance is transferred to the capacitor C of the first surge absorption circuit.
u, and the charging voltage of the capacitor Cu tries to rise above the DC power supply voltage value Ed, but in this case, according to this embodiment, the energy stored in the reactor Lu and the wiring inductance is reduced by the load current. During the transition period when the diode D1 is about to flow to the diode Du side, the newly inserted diode D1 becomes conductive, and the above energy is refluxed through the path between this diode D1 and the reactor Lu, and all the energy stored in this reflux path is consumed. Ru.

Therefore, the voltage of the capacitor Cu never rises above the power supply voltage value Ed, and the capacitor voltage is maintained at the power supply voltage value Ed while the element Su is OFF.

In such a state, if element Su is turned on again to commutate the load current to the U arm, when element Su is turned on, capacitor C
The charge stored in u is discharged through the element Su, and during this discharge, according to the present application, the discharge time constant τ of the capacitor Cu and the resistor Ru is set to 1, which is the reciprocal of the frequency f of the inverter, as described above. Since the constant of Cu-Ru is predetermined in advance so as to have a smaller value than At the time of re-extinguishing, the charging voltage is zero V.

Therefore, like the conventional device shown in FIG. 1 explained in FIG. 4, the capacitor voltage takes on the initial value Eo, and dv/
dt is never a threat to the device.

In the embodiment of FIG. 5, the diode D1. Even if a resistor as shown by the broken line is connected in series with D2, the desired purpose can be achieved in the same way as in the circuit example using only a diode, but in such a case, the discharge time constant of the reactor, resistor, and diode is Each constant may be selected so as not to reduce the effect of the reactor by making it small.

As described above, in the present invention, the dv/dt suppression at the time of turn-off of the GTO element is carried out by the conventionally well-known surge absorption circuit,
The peak value of dv/dt was suppressed by a newly installed circuit, and the relationship between the C-R discharge time constant of the surge absorption circuit and the inverter frequency was considered to be in a certain regulated relationship. Because of this, it has various effects as shown below.

(2) Since the suppression of dv/dt and its peak value are carried out separately, the most effective surge suppression can be achieved and is particularly suitable for high frequencies.

■ Since destruction of elements due to switching losses etc. can be completely prevented, it is possible to realize a highly reliable device that can operate stably even in unstable circuits such as vibration loads.

(2) Even if a new circuit is added to suppress the peak value of dv/dt, the circuit configuration is kept as simple as possible, so it is possible to realize a device that is very advantageous in terms of cost.

[Brief explanation of the drawing]

Figure 1 is a typical inverter circuit example using a gate turn-off thyristor, Figure 2 is a voltage-current waveform diagram when the gate turn-off thyristor is OFF, and Figure 3A is a conventional circuit example of a gate turn-off thyristor. ON
Figure 3B is a voltage-current waveform diagram showing the relationship between the load current, CR release load current, element voltage, and current flowing through the element. FIG. 4 is a voltage waveform diagram showing the capacitor charging voltage when the inverter frequency is smaller than the CRR time constant in a conventional circuit example, and FIG. 5 is an example of an implementation according to the present invention. A specific circuit diagram showing an example. 1.2 is a surge suppression circuit, Lu-Lw, Lx~Lz beam handle, Su~Sw, 5x-8z is a gate turn-off thyristor, C is a capacitor, R is a resistor, D is a diode, and Ed is a DC power supply.

Claims (1)

[Scope of Claims] 1 Positive side reactor - first gate turn-off thyristor, second gate turn-off thyristor, negative side reactor connected in series, and a plurality of sets of arms connected in parallel,
This is a bridge inverter that extracts the load from each bridge point between the first gate turn-off thyristor and the second gate turn-off thyristor of each arm, and the first surge absorber consists of a capacitor resistor and a diode between the terminals of each gate turn-off thyristor. By connecting circuits in parallel, this circuit suppresses dv/dt at turn-off, and the positive and negative electrodes suppress di/dt at turn-on to protect the inverter. Therefore, a second surge absorption circuit consisting of a diode is connected in parallel to the positive side reactor and negative side reactor of each arm, and this circuit controls the peak value of dv/dt at turn-off. A method of protecting an inverter using a characteristic gate turn-off thyristor. 2. A method for protecting an inverter using the gate turn-off thyristor according to claim 1, wherein a resistor is connected in series with the diode of the second surge absorption circuit. 3. The relationship between the discharge time constant τ of the capacitor resistor of the first surge absorption circuit that suppresses dv/dt at turn-off and the frequency f of the inverter is adjusted so that the discharge time constant τ satisfies the relationship τ<-. A method for protecting an inverter using a gate turn thyristor according to claims 1 or 2, which comprises selecting a constant.