JPS5824879A - Converter driving circuit for electronic time piece - Google Patents

Abstract

PURPOSE:To return the vibration phase to the normal state quickly by changing the drive pulse width and the phase at the normal time in linkage with a switch circuit employing a CMOS transistor when the amplitude and the phase of a converter are above or below the preset value. CONSTITUTION:When the vibration phase of a converter advances with respect to a force drive signal 58 due to disturbance, the waveform of the induced voltage is as shown by the waveform 51b. A phase advance difference detection circuit 22 whose input is a phase advance reference signal phiS1 and not-output -A of the detection circuit output A operates to produce pulses 69 from the output B to set the output D of phase advance difference memory circuits 23 and 24 at ''1''. Phase advance driving pulses phiS2 pass a switching circuit 25 and pulses -phiZ develop at the output G to be applied to the input J of an AND circuir 40. Since the waveform 58 was previously applied to the input K, the output L of a pulse selection circuit is as shown by the waveform 71. In short, this generates an output voltage equivalent to two times as large as the pulse width of pulses extended by 1/16 second in the advance direction from those at the normal time which causes a drive current 72 to flow through a drive coil 43. Thus, the vibration phase of the converter is returned quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a mechanical oscillator drive circuit for a balance wheel, a vibrator, etc. used in an electronic timepiece, particularly a quartz wristwatch.

In electronic watches, in the case of a resonant converter that forcibly drives a mechanical resonator such as a balance wheel or a tone bar by an electric signal from a reference signal source such as a crystal oscillator circuit, the vibration amplitude and reference drive of the resonant converter are It is necessary to maintain the phase difference between the signal and the vibration phase within a certain range in order to accurately convert the motion to the wheel train system in synchronization with the reference signal.

Generally, when a resonant converter is forcibly driven, the vibration amplitude and phase of the resonant converter are held constant by the voltage, current, frequency, and pulse width of the drive input signal. However, disturbances such as shocks during carrying cause fluctuations in the amplitude and phase of the resonant transducer, impairing the stability of the motion conversion effect.

Conventionally, in order to stabilize vibration vibration 1] against disturbances,
It is known to provide a control circuit so that the pulse width of the drive input signal changes in response to changes in the vibration amplitude.

However, since the conventional technology only has a vibration amplitude control effect and no phase control effect, it cannot immediately respond when the vibration phase changes with respect to the reference drive signal due to disturbance etc.
If there is a large change, synchronization may occur, which may impair the stability of the motion conversion effect and cause it to stall.

The present invention eliminates the above-mentioned drawbacks, and works in conjunction with a switch circuit using C/MOS transistors to change the normal drive nockle width when the amplitude and phase of the converter exceeds or falls below a preset value. and a circuit configuration that operates to change the phase.

The present invention will be explained in detail below with reference to the drawings.

In FIG. 1, 10, 11 and 12 are first signal generation circuits composed of flip-flop circuits that divide the output of a crystal oscillator or the like by appropriate percentages, 10a is an input side, and 12
a is the output side of the flip-flop circuit 12, φ3, φ
If the frequency of 3 is 16Hz, flip-flop circuit 1
The frequency of the output φ2, φ2 of the flip-flop circuit 10 is 32Hz, and the frequency of the output φ1, φ1 of the flip-flop circuit 10 is 1464Hz.
and the input φo1 φ of the flip-flop circuit 10. The frequency of is 128 Hz.

(3) 13.14.15 and 16 are first reference signal generation circuits for obtaining the first reference signal φ, and 3+13 receives the input φo1 of the flip-flop 10 and the output φ1 of the fritz flop 7''10. AND circuit, 14 is the input φo1 of the flip-flop 10, the flip-flop 7″
11-tAN with an AND circuit that inputs the output φ1 of 10
It is an OR circuit that receives the outputs of D circuits 13 and 14 as input,
16 is the output φ2 of the flip-flop 11, and the OR circuit 15
This is an AND circuit whose inputs are the output of the flip-flop 12 and the output φ3 of the flip-flop 12.

17 is a 22nd reference signal generation circuit for obtaining the second reference signal φ;
This is an AND circuit whose inputs are the output φ2 of the 1111 flip-flop 12 and the output φ3 of the flip-flop 12.

18 is the 11th J set/? In order to obtain the pulse φ, the output φ1 of the flip-flop 10, the output φ2 of the flip-flop 11, and the output φ2 of the flip-flop 7”1 are used.
This is an AND circuit (4) which takes the output φ3 of 2 as an input.

19 is the second waveform conversion circuit for obtaining the second reset pulse φ, and the output φ1 of the flip roller 7"10
Output φ2 of flip flop f11, flip flop 1
This is a NAND circuit that receives the output φ3 of 2 as an input.

20 is a second signal generation circuit that obtains phase advance driving pulses; 7;
NAND with input φo1 of flip-flop f1.0, output φ11 of flip-flop 10, output φ2 of flip-flop 11, and output φ3 of flip-flop 7'12.
It is a circuit.

In FIG. 2, 30 is a detection circuit, 31 is a reset circuit, 33.34 is set to "1" according to the output of the detection circuit 30, and is set to "O" by the first reset pulse φ.
Reset to old Set Inverse Fritzoflots f (R8T
FF ), 35 is an inverter, 36.37 is an AND circuit, and 38 is a NOR
The circuit operates as an input switching circuit that receives the outputs φo1 to φl of the first signal generation circuit as input, and forms part of a drive/e pulse selection circuit to be described later. Detection circuit 30, amplitude storage circuit 33.34, input switching circuit 35.36.37.38
Configure the amplitude control system.

39 is a NAND circuit, and terminal 0 is the output of the switching circuit.
, terminal IFi signal φ11, terminal 2 is connected to signal φ2, and terminal 3 is connected to signal φ3, forming a waveform conversion circuit.

31 is an inverter; 22 is a NAND circuit whose inputs are the first reference signal φ and the negative A of the output A of the detection circuit 30; a leading phase difference detection circuit;
．． 24 corresponds to the output of the advanced phase difference detection circuit 22.
Re5et old Set Inverse frig float f (R8T
A first switching circuit 25 is composed of the outputs of the leading phase difference storing circuits 23 and 24, and a NAND circuit whose input is the phase leading drive/('rus φ2). do.

The advanced phase difference detection circuit 22 and the advanced phase difference storage circuit 23
．． 24, the switching circuit 25 constitutes an advanced phase control system 44.

26 is a NAND circuit which receives the second reference signal φ and the negative A of the second output A of the detection circuit 30, and constitutes a lagging phase difference detection circuit; Re5et Set Inverse
A lagging phase difference storage circuit 29 constituted by a flip-flop (R8T FF) is a lagging phase difference storage circuit 27.
A second switching circuit is constituted by a NAND circuit whose inputs are the output E of 28 and the second reset pulse φ.

The lagging phase difference detection circuit 26 and the lagging phase difference storage circuit 27
．． 28, a switching circuit 29 constitutes a delayed phase control system.

32Fi is an AND circuit which receives the output N of the second switching circuit 29 and the first reset pulse φ, and the output IH is connected to the NAND circuit of the amplitude storage circuits 33 and 34.

This is an AND circuit that receives the output G of the 40Fi switching circuit 25 and the output K of the waveform conversion circuit 39 as inputs. (7) A drive pulse selection circuit is constituted by the input switching circuit consisting of the first switching circuit 25, the second switching circuit 29, the inverter 35, and the dart circuits 36, 37, and 38, the waveform conversion circuit 39, and the dart circuit 40. .

41. 42 is a drive inverter, and 43 is a drive coil.

3 and 4 are waveform diagrams illustrating the operation when the electromechanical converter is operating normally, in which 51 is the voltage waveform induced in the drive coil 43, 52 is the amplitude detection voltage level, and 53 is the waveform diagram illustrating the operation when the electromechanical converter is operating normally. The output waveform of the detection circuit 30, 67, shows the current waveform of the drive coil.

FIG. 5 is a waveform diagram illustrating the operation when the vibration phase of the electromechanical converter advances, and shows the output B of the leading phase difference detection circuit 22.
69 indicates the state in which the phase advance control circuit is operating.

FIG. 6 is a waveform diagram illustrating the operation when the imaging phase of the electromechanical converter is delayed, and shows the output C of the delayed phase difference detection circuit 26.
γ4 indicates the state in which the slow phase control circuit is operating.

Next, the effect will be explained.

(8) 16 Hz, i/'16 to converter drive coil 43
When a drive signal with a period of a certain pulse width is applied and the device is in a steady state, the voltage and current waveforms shown in FIGS. 3 and 4 are shown.

The drive coil 43 generates an induced voltage waveform due to the electromagnetic action between the drive coil 43 and a permanent magnet provided in the balance type resonance converter. 51' and 51'' indicate the induced voltage at the point where the induced voltage is maximum, that is, at the two maximum speed points during one vibration when the magnet of the converter and the drive coil 20 overlap. In a converter designed to generate a forced driving force when 51'l, the drive circuit of the present invention uses induced voltage 51' to detect the amplitude and phase difference.

The detection circuit 30 in FIG. 2 is composed of complementary MOS transistors, and when the supply voltage is 1.5V, the threshold voltage can be set to about 0.75V, and the peak induced voltage of the drive coil 43 during steady state can be set to 1. If set to about .0V, the induced voltage will have the waveform shown in FIG. 3X. Therefore, at this time, the voltage at the detection level 52 is 0.75V, and the head 51' of the induced voltage crosses the detection level 52 at 315 points.

Therefore, between ah shown in FIG. 3, the detection circuit 30 is inverted, and the output waveform at point A in FIG. 2 becomes as shown in FIG. 3, 53.

When the output F of the amplitude memory circuits 33 and 34 is set to ``1'' by this pulse, the output of the inverter 35 becomes 50.
'', the output φ1 of the first signal generation circuit cannot pass through the AND circuit 36.The output φ0 of the first signal generation circuit
passes through the AND circuit 37 and becomes the output of the input switching circuit 38 ■
is φ. becomes. Therefore, the input terminal 0 of the NAND circuit 39
waveform 54, i.e., φo1, waveform 55, φ7, at terminal 2, waveform 56, i.e., φ2, and waveform 57, i.e., the first waveform at terminal 3.
The output φ3 of the signal generating circuit is applied to the output terminal K.
The las width becomes 1/16 and the output waveform shown in FIG. 3 is obtained. On the other hand, in the steady state, since the phase advance control circuit does not operate, the output G is 1, so the input J of the AND circuit 40 is 1, and the output of the AND circuit 40, that is, the output of the signal selection circuit is 58. The darkness will appear.

Thus, in a steady state where the induced voltage 51 exceeding the detection level 52 is generated, the pulse selection circuit outputs the signal 58 at a predetermined frequency of 16 Hz.

It is kept at 1/16 during the pulse. Further, the amplitude memory circuit 33.
34 NAND circuits 33 through the AND circuit 32
z9 pulse φ (Fig. 4 (7) 164) is applied, and the amplitude memory circuit output F is reset to "0" every time a drive pulse is applied, and the set pulse is applied to the input terminal A. The state is returned to the state before entering.At this time, the lagging phase control circuit is not operating, so the output N
1", and φR1 passes through the AND circuit 32 and becomes N
It is applied to the AND circuit 33.

On the other hand, when the vibration phase of the converter advances with respect to the forced drive signal 58 due to disturbance etc., the induced voltage waveform becomes as shown in 51b as shown in FIG. The leading phase difference detection circuit 22 which inputs the negative output A1 of is operated, and its output B becomes 69, which is set to the output Dn %% 1 of the leading phase difference storage circuit 23.24, for the leading phase drive.・
The mother pulse φ2 (59 in FIG. 3) passes through the first switching circuit 25, and φ2 (70 in FIG. 5) appears at the output G, and A
ND circuit circuit 4 people 0 will be. Since the waveform 58 is applied to the input K, the output waveform of the pulse selection circuit is as shown in 71. In other words, an output voltage is generated that is the steady state pulse extended by 1/16 sec in the forward direction and twice the ξ pulse width, and a drive current 72 flows through the drive coil 43, and its relationship with the induced voltage 51b is as shown in FIG. become. As a result, the resultant force doubles and increases in the phase advance direction, so the driving force acts effectively and the advanced vibration phase is delayed and rapidly returned to a steady state.

Furthermore, when the vibration phase of the converter lags behind the forced drive signal 58, the induced voltage waveform becomes 51c as shown in FIG.
The second reference signal φ having a different phase from the first reference signal and the negative of the output A of the detection circuit 2 are operated, and the delayed phase difference detection circuit 26 operates, and its output C is 74 Therefore, the outputs E of the slow phase difference memory circuits 27 and 28 are set to ``1'', the second reset signal φR2 (65 in FIG. 4) passes through the NAND circuit 29, and the output NK becomes (11). φ (75 in FIG. 6) appears, is applied to the AND circuit 322, and its output H becomes like 76. That is, A
The amplitude memory circuit 33, 3 is set to ``1'' by
The output F of 4 is reset to "0" again, and the output I of the switching circuit becomes φ1. This is applied to the input terminal 0 of the waveform conversion circuit 390, and the waveform 55, that is, φ1, is applied to the terminal 1, and the output I of the switching circuit becomes φ1.
Since the waveform 56 or φ2 is applied to the terminal 3 and the waveform 57 or φ3 is applied to the terminal 3, the output waveform is as shown in 77, and since the phase advance phase control circuit is not operating, its output Gflゝゝゝ1", that is, the input J of the AND circuit 40
Therefore, the output voltage of the voltage selection circuit is as shown in 77. In other words, the normal voltage is extended in the direction of 1/□6SeC delay, and an output voltage twice the voltage is generated.
A drive current 78 flows through the drive coil 43, and its relationship with the induced voltage 51c is as shown in FIG.

As a result, the input is doubled and also increases in the direction of the slow phase, so the driving force acts effectively and the delayed vibration phase is advanced and rapidly returned to the steady state.

Here, the vibration phase of the converter is the first reference signal φSl.

(12) and the second reference signal φ after a certain period of time. will be compared.

When the vibration amplitude of the converter decreases and therefore the voltage 51a induced in the drive coil 43 becomes lower than the detection level 52, the detection circuit 30 does not operate and the output terminal AK does not detect /- and Q pulses. On the other hand, since the lagging phase control circuit also does not operate, its output N is always 91", and the reset sorus φ
(Fig. 6 64) is normally connected to R+ by AND circuit 32'ff: amplitude storage circuit 33, 3 through
Since the NAND circuit 33 of No. 4 is connected to the human power I (K), the output of the amplitude memory circuits 33 and 34 is reset to Fflゝゝ0''. In other words, the state is the same as when the vibration phase is delayed, and the output of the switching circuit ■ becomes φI, which is applied to the input of the waveform conversion circuit 390, and the waveform at its output becomes as shown in 77. Since the phase advance phase control circuit is not operating, its output G is ``1'', that is, the AND circuit 40 The input J is ``1'', and the output of the pulse selection circuit is 77. That is, twice the output voltage is generated during the steady pulse, and the drive coil 43 has twice the drive. current flows,
The input is doubled and the reduced amplitude is quickly pulled back to steady state.

In this embodiment, the pulse 1 in the case of using a Tenzo type resonant converter has been described, but it is clear that the present invention may be applied to driving a converter of a tuning fork vibrating piece or the like. Also,
The present invention can be easily applied to pulse smoke and the like. In this case, the drive pulse width may be controlled by detecting the transient amplitude state of the rotor immediately after the end of drive/gurus application. In addition, in this embodiment, the synchronization power to the converter is 16 Hz 1
/16 pulses, and when the vibration is abnormal (phase advance, phase lag, and amplitude decrease), the width is set to zero.
In general, /4'rus width%n (n=1.2,...
), and it is also clear that it is possible to create a circuit configuration that expands the pulse width by a factor of 1 or more, such as 2 times or 4 times, in the event of an abnormality. The driving frequency is also not limited to 16 Hz. Although the drive coil is used as the input to the detection circuit, it is clear that an additional detection coil may be provided.

One of the effects of the present invention is that when the vibration phase of the converter (15) is delayed due to disturbance etc., the pulse 111 is
Since it doubles and extends in the delay direction, the vibration phase quickly returns to a steady state and the operation becomes stable.

Another effect is that when the vibration phase of the converter advances,
Since the vibration phase d] is twice that of the steady state and extends in the advancing direction, the vibration phase is quickly returned to the steady state and the operation becomes stable.

Another effect is that when the amplitude of the converter decreases and becomes smaller than the detection amplitude, the amplitude during the drive pulse is twice that of the steady state, so the amplitude quickly returns to the steady state and the operation becomes stable. That's true. Furthermore, one of the effects of using the drive circuit of the present invention is that the entire MO8 is implemented and the circuit becomes extremely small.

[Brief explanation of drawings]

Figures 1 and 2 are main configuration block diagrams of an embodiment of the present invention, Figures 3 and 4 are illustrations of the operation of the circuit in steady state, and Figure 5 is when the vibration phase of the converter advances. FIG. 6 is an explanatory diagram of the operation when the vibration phase is delayed. (16) 44... Advance phase control system 45... Lagging phase control system 33.34... Amplitude storage circuit 30... Detection circuit 10 .11.12.20...Signal generation circuit 1st
Figure No. 4 @ 0 61 9 60 ψ259

Claims (1)

[Claims] In a converter drive circuit that drives a converter by supplying drive pulses to both ends of a drive coil of the converter via a drive inverter, a signal generating circuit that generates a plurality of pulse signals having different widths; A drive pulse selection circuit that selectively supplies a pulse signal to a drive inverter; and a detection circuit that detects an induced voltage of the drive coil connected to one end of the drive coil, and the detection circuit detects when a drive pulse is applied. By detecting the induced voltage while avoiding the
A converter drive circuit for an electronic watch characterized by supplying a drive signal with a large pulse width.