JPS5824241A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS5824241A JPS5824241A JP56123260A JP12326081A JPS5824241A JP S5824241 A JPS5824241 A JP S5824241A JP 56123260 A JP56123260 A JP 56123260A JP 12326081 A JP12326081 A JP 12326081A JP S5824241 A JPS5824241 A JP S5824241A
- Authority
- JP
- Japan
- Prior art keywords
- product term
- array
- left half
- term lines
- fpla
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
Abstract
Description
【発明の詳細な説明】
本発明はプログラム情報がマトリクス形式で設定された
１例えばフィールドプログラマブルリシックアレイ（以
下、ＦＰＬＡと記す）を有し、マ（リクス接点に設けら
れた半導体素子もしくは導体の接続・非接続により所望
の論理を実現する集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention has a field programmable lithic array (hereinafter referred to as FPLA) in which program information is set in a matrix format, The present invention relates to an integrated circuit device that realizes desired logic through connection and disconnection.
近年、高集積化技術の進歩に伴ってＦＰＬＡも大容量の
ものが開発されているが、一般に容量が大きくなるに従
って７レイの利用効率が落ちる傾向にあり、これがＦＰ
ＬＡの大容量化を抑える一因となっている。特にユーザ
が自由に独自のプレグラムを書き込むような汎用のＰＬ
ムにおいては、＊適容量の判断がつかないために、容量
不足や無駄を生じていた。In recent years, with the advancement of high-integration technology, large-capacity FPLAs have been developed, but as the capacity increases, the utilization efficiency of 7 rays tends to decline, and this
This is one of the reasons for suppressing the increase in LA capacity. Especially general-purpose PLs where users can freely write their own programs.
In systems, it was difficult to judge the appropriate capacity, resulting in insufficient capacity and waste.
本発明の目的は、ＰＬムの構造に改良を加えてその使用
効率を高めた集積回路装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device in which the structure of a PL is improved to increase its usage efficiency.
このため本発明はアレイ部を複数個の独立な組に分割し
て必要なアレイ部のみを選択的に活性化する手段を具債
することを特徴とする。For this reason, the present invention is characterized by including means for dividing the array section into a plurality of independent groups and selectively activating only the necessary array section.
この結果、ひとつのＰＬＡ上で複数個の独立な論理回路
構成を実現することが可能となり、アレイの使用効率を
向上させ、より一層の高集積化を図ることができる。As a result, it becomes possible to realize a plurality of independent logic circuit configurations on one PLA, improving the efficiency of use of the array and achieving even higher integration.
以下１本発明を図面を用いて詳細Ｅｌ！明する。The following is a detailed explanation of the present invention using drawings! I will clarify.
第１図は従来ｏＦＰＬムのプロッタ図である。図に示し
たＦＰＬＡはアンドアレイ１−オアアレイ２の二段ＩＩ
Ｉ造をなし、！トリクス接点の接１１（４，９）−非接
続（３，８）によりアンドアレイ１では任意の入力５０
組み合せ論ｉｉ＊を、又オアアレイ２ではそれらの出力
の論理和な実現する。また、１３１５．１７は書き込み
用デコーダであり、２１は書き込み内容の検査用デコー
ダである。読み出しモード（逓當０動作モード）では積
項線７はすべてデコーダ回路２１により抵抗を介して電
源に接続されており、この状態をすべての檀ｉ、ｉｉｉ
が活性であると表現する。検査モード時には、書き込み
内容の検査用デコーダ２１に任意のアドレス入力２０を
加えると、そのアドレスに対応した積項線１本が選択さ
れ活性となり、他の積項線はすべて接地レベルとなる。FIG. 1 is a plotter diagram of a conventional oFPL system. The FPLA shown in the figure is a two-stage II of AND array 1-OR array 2.
I built it! Due to the contact 11 (4, 9) - disconnection (3, 8) of the trix contact, any input 50 in AND array 1
The combinatorial logic ii* is realized by the OR of their outputs in the OR array 2. Further, 1315.17 is a decoder for writing, and 21 is a decoder for checking written contents. In the read mode (zero operation mode), all product term lines 7 are connected to the power supply via resistors by the decoder circuit 21, and this state is
is expressed as active. In the test mode, when an arbitrary address input 20 is applied to the write content test decoder 21, one product term line corresponding to that address is selected and activated, and all other product term lines are at ground level.
この状態を選択された以外のすべての積項線が非活性で
あると表現する。非活性な積項線は、いかなる入力が加
えられても出力にはなんらの影響も与えず、あたかもそ
の積項線上のすべてのマ）９クス接点が非接続であるか
の機に動作する。This state is expressed as all product term lines other than the selected one being inactive. An inactive product term line has no effect on the output no matter what input is applied, and operates as if all the contacts on the product term line were disconnected.
ところで、第１図の回路では、アンドアレイはその１／
４程度しか利用されておらず、ＦＰＬＡの長所が十分に
生かされていない。By the way, in the circuit shown in Figure 1, the AND array is 1/
Only about 4 are used, and the advantages of FPLA are not fully utilized.
と０＠りの部分を効率的に活用できるようにした例が第
２図であり、これは本発明の一実施例である。An example in which the 0@ portion can be used efficiently is shown in FIG. 2, which is an embodiment of the present invention.
第２図は、１つのＦＰＬＡを積項線方向に２分し、２つ
の独立な回路構成を１つのＦＰＬ人上に実現した例であ
る。Ｉ！２図に示す回路は、従来のＰＰＬＡと比較して
、書き込み内容の検査用デコーダ２１’に新たな機能を
付加している。すなわち書き込み内容の検査用デコーダ
を２分して制御信号２３’、２４’により左半分右半分
の積項線をそれぞれ独立に制御可能としている。例えば
％制御信号２３′が入力される（ソフト制御でもスイッ
チ１１１Ｉ′ｆＩＪでも−よい）と、それによって左半
分のデコーダ出力が積項線へ転送されるようにゲートを
開くようにすればよい。このようにして左半分の積項線
を活性にし右半分の積項線を非活性にすれば、左手分の
積項線上にプルグラムされた回路のみが動作し、逆に左
半分の積項線を非活性にし右半分の積項線を活性にすれ
ば右半分の積項線上にプルグラムされた回路のみが動作
する。またすべての積項線を活性にすれば従来のＦＰＬ
Ａと等しい容量のプ璽グラム動作となる。FIG. 2 is an example in which one FPLA is divided into two in the product term line direction, and two independent circuit configurations are realized on one FPL. I! The circuit shown in FIG. 2 has a new function added to the written content inspection decoder 21' compared to the conventional PPLA. That is, the decoder for checking written contents is divided into two parts, and the product term lines of the left half and the right half can be controlled independently by control signals 23' and 24'. For example, when the % control signal 23' is input (soft control or switch 111I'fIJ may be used), the gate may be opened so that the left half decoder output is transferred to the product term line. In this way, by activating the product term line on the left half and deactivating the product term line on the right half, only the circuit programmed on the product term line in the left hand will operate, and conversely, the product term line in the left half will operate. If you deactivate and activate the right half product term line, only the circuit programmed on the right half product term line will operate. Also, if all product term lines are activated, the conventional FPL
The program operates with a capacity equal to A.
第２ｖＩｉでは、２分割の例を挙げたがそれ以上の分割
も同様に可能である。In the second vIi, an example of two divisions is given, but more divisions are also possible.
以上説明した様に本方式は従来のＦＰＬＡに若干の回路
を付加するだけで、１つのＦＰＬＡ上で複数個の独立な
論理回路を実現することが出来る。さらに本方式はこれ
まで発表された同等の機能を持つ畳み込みＰＬ人の持つ
以下の様な不具合（１）マスクＰＬムにしか適応出来な
い、 （２）入力端子数が従来ＯＰＬ人の２倍必要であ
る。も解消出来る。As explained above, in this method, a plurality of independent logic circuits can be realized on one FPLA by simply adding a few circuits to a conventional FPLA. Furthermore, this method has the following problems with convolutional PL systems that have the same functionality as previously announced: (1) It can only be applied to masked PL systems; (2) It requires twice the number of input terminals as conventional OPL systems. It is. can also be resolved.
第１ｍは従来のＦＰＬＡのブロック図、第２ｗＪは本発
明の一実施例によるＦＰＬＡのプレツタ図である０The 1st m is a block diagram of a conventional FPLA, and the 2nd wJ is a preset diagram of an FPLA according to an embodiment of the present invention.
Claims (1)
アレイ状の回路を少なくとも２個のプ四りクに分割する
手段と、分割された個々のブロックを独立に制御して書
き込まれた情報に従って処理を実行させる制御手段とを
有するプｐグフム論１１回路を含むことを特徴とする集
積回路装置。M) Means for dividing an array-like circuit having a large number of information writing contacts arranged in a nine-square shape into at least two blocks, and information written by independently controlling each divided block. 1. An integrated circuit device comprising: an integrated circuit device having a control means for executing processing according to the PPGHM logic 11 circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56123260A JPS5824241A (en) | 1981-08-05 | 1981-08-05 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56123260A JPS5824241A (en) | 1981-08-05 | 1981-08-05 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5824241A true JPS5824241A (en) | 1983-02-14 |
Family
ID=14856155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56123260A Pending JPS5824241A (en) | 1981-08-05 | 1981-08-05 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5824241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868426A (en) * | 1986-04-07 | 1989-09-19 | Nixdorf Computer Ag | Programmable logic array having connectable matrices |
-
1981
- 1981-08-05 JP JP56123260A patent/JPS5824241A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868426A (en) * | 1986-04-07 | 1989-09-19 | Nixdorf Computer Ag | Programmable logic array having connectable matrices |
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