JPS5823994B2 - Test signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a test signal generator used when testing image transmission systems such as televisions and facsimiles. The present invention relates to a test signal generating device that can easily make a determination.

Conventionally, to test an image transmission system, a transmitter reads a special test chart, reproduces the receiving surface on a receiver via a transmission path, and tests various patterns included in the test chart 1, etc. The performance of the image transmission system was evaluated by examining reproducibility.

The test charts used in such cases are characters,
It is structured to be convenient for evaluating overall performance such as resolution using striped patterns, shading, etc., but it is also easy to use to evaluate the distortion of the received image that is affected by the frequency characteristics of the transmission system and various other characteristics. could not be evaluated.

An object of the present invention is to provide a test signal generating device that eliminates the above drawbacks and allows easy determination of the reproducibility of a received image, which is affected by the performance of the transmission system, on the received image.

According to the present invention, there is obtained a test signal generating device characterized in that an index frame of constant scan lines including an index pulse and a test frame of constant scan lines including a test pattern are synthesized serially in time. .

Next, an embodiment of the test signal generating device according to the present invention will be described in detail with reference to one drawing.

FIG. 1 is a block diagram showing the basic configuration of an apparatus according to the present invention.

In the figure, 1 is a control circuit, 2 is an index frame generation circuit, 3 is a test frame generation circuit, and 4 is a synthesis circuit.

The control circuit 1 is a part that determines generation conditions for the index frame generation circuit 2 and the test frame generation circuit 3 in chronological order.

As will be described later, the index frame generation circuit 2 is a section that generates a pattern that serves as a reference for a test signal, and the test frame generation circuit 3 is a section that generates a pattern of a test signal.

The synthesis circuit 4 is a part that synthesizes the signals generated by the index frame generation circuit 2 and the test frame generation circuit 3 and converts them into a serial signal.

In the above, the frame lengths of the signals generated by the index frame generation circuit 2 and the test frame generation circuit 3 are selected to correspond to, for example, the lifetime scanning period of the image.

The index frame includes an index pulse, and the test frame includes a signal pulse for a test pattern for checking the reproducibility of a received image.

The test frame includes, for example, one of each of a plurality of pulses having different time widths, and a test pattern is formed by repeating the test frame signal a plurality of times.

In addition. In addition to the index pulse and the test pattern signal pulse, a synchronization signal can be added to each of the two frame signals for synchronization.

FIG. 2 is a block diagram showing one embodiment of the test signal generator according to the present invention.

In this figure, the clock signal generation circuit 5 is specifically a clock signal generator 50 as seen in FIG. 2C.
and a digit counter 51 in the form of a flip-flop circuit connected in cascade, for example, in order to receive the clock signal and obtain a sequentially counted output.

As an output signal of this clock signal generation circuit 5, the clock signal of the clock signal generator 50 is applied to the digital counter 51, and at the same time, it is applied as a clock signal to the same test frame generation circuit 3 as described in FIG. Supplied.

Further, from the disicle counter 51, as shown in FIG. 2C.

The inverted values of the outputs of multiple flip-flops in the subsequent stage are outputted as a frame signal via an AND circuit, and the outputs of all flip-flops are sent through another AND circuit to generate a count corresponding to the position of the index. Extract as output.

Among these output signals, the frame signal is supplied to the index frame generation circuit 2 and the control circuit 1, and the count output corresponding to the position of the index is supplied to the index frame generation circuit 2.

An example of the operation waveforms of the frame signal and the count output corresponding to the position of the index is as shown in the time chart of FIG. 2d.

In this chart, the numbers appended to the waveforms indicate the corresponding numbers of count pulses counted from the point of repetition of the frame signal.

The control circuit 1 is. Receiving a frame signal from the clock signal generation circuit 5, a 1/2 frequency dividing circuit extracts signals of alternately selected frame lengths to two output terminals,
As a result, the index frame generation circuit 2 and test frame generation circuit 3 are driven.

As shown in the block diagram of FIG. 2a, the index frame generation circuit 2 includes, for example, an OR circuit 20 and an AND circuit 21.
and a shaping circuit 22, which outputs a power Wundt output corresponding to a required position obtained from the digital counter of the clock signal generating circuit 5, and a frame signal from the clock signal generating circuit 5, which is generated by shaping the frame signal by the shaping circuit 22. In response to the synchronization signal, these are applied to the two inputs of the OR circuit 200, and the output and the frame length signal for switching between the index frame and the test frame from the control circuit 1 are applied to the AND circuit 21. An index frame signal is obtained from its output.

The test frame generation circuit 3 is constructed as shown in the block diagram of FIG. 2b, one specific example of which is shown.

In the figure, numerals 30 and 31 each indicate a digital counter constructed by a flip-flop circuit. When a frame length signal is applied from the control circuit 1 through the terminal A, the counter 30 receives the required test pulse. Outputs a count pulse corresponding to the position of the leading edge of the width,
Counter 31 outputs a count pulse corresponding to the position of the trailing edge of the width of the test pulse.

32 is a start point setting circuit that determines the position of the test pulse to be applied to the first frame, and this output determines the position of the test pulse to be applied to the first frame.

Digital counter 3 to generate the first test pulse
0 and 31 are driven.

The example in Fig. 2b shows the case where there is one test pulse in the test frame, as shown in Fig. 3, and the switching applied from terminal A every time a test frame occurs. The digital counters 30 and 31 are set with new information by the signal.

The digital counters 30 and 31 are, for example,
It consists of a down counter, and when a switching signal is given from terminal A, the initial value is set by the output given from the start point setting circuit 32, and therefore it is cleared every frame. There's no need.

33 and 34 are comparison circuits for detecting coincidence of two input pulses, respectively.

The output pulse of the digital counter 30 and the clock signal led from the clock signal generation circuit through the terminal B are applied to the comparison circuit 33, and a match is detected and outputted.

Similarly, the output pulse of the digital counter 31 and the count pulse from terminal B are applied to the comparison circuit 34,
The match is printed.

35 is a flip-flop circuit, which causes the Q output to rise in response to the leading edge pulse from the comparison circuit 33 applied to the set input terminal S, and causes the Q output to rise in response to the trailing edge pulse from the comparison circuit 34 applied to the reset input terminal R. let it fall.

31 is a waveform shaping circuit for receiving a two frame length signal to obtain a pulse of a necessary width, and is used as a synchronizing signal.

Output of flip-flop circuit 35 and waveform shaping circuit 37
The output of is applied to the OR circuit 36, and the output is extracted to the output terminal C as a test frame signal.

Referring again to FIG. 2, both frame signals from the index frame generation circuit 2 and the test frame generation circuit 3 are alternately applied to the synthesis circuit 4 and are obtained as an output in time series form.

This output signal is applied to the amplitude modulation circuit 7, amplitude-modulated by the local signal from the carrier wave oscillation circuit 6, and sent out to the transmission line.

Figure 3 shows an example of the relationship between the output waveform of the test signal generator to be transmitted and the pattern on the receiving screen. It is something that

In addition, figure b is an enlarged view of the part indicated by the chain line in the center of figure a, and for easy identification there are multiple parts m
' represents a pixel caused by the index pulse m in the index frame, and a plurality of parts t' with different widths that alternately exist between the plurality of m' parts are test frames constituting the test pattern. It shows pixels based on signals 11, 12, etc. within.

Although these pixels are shown in the figure for ease of distinction, they would actually be seen by black dots and black lines, respectively.

Figure C shows only four frames out of the waveform diagrams of a plurality of index frames and test frames necessary to draw diagram b.

In this waveform, index frames M1 and M2 are.

Each of them is composed of the same synchronizing signal P and index pulse m.

Further, the test frame T1 is composed of a synchronizing signal P and a signal pulse t1 of a test pattern, and the test frame T2 is composed of a synchronizing signal P and a signal pulse t2 of a test pattern.

Although only tl and t2 are shown here as the signal pulses of the test pattern, they are actually a collection of multiple pulses, and these pulse widths are changed depending on the received image to be expressed.
You can also change its position.

FIG. 4 shows an example of the output waveform of the synthesis circuit 4 in the test signal generator shown in FIG.

As shown in FIG. 2a, the index frame generation circuit 2 and the test frame generation circuit 3 are alternately controlled to generate by the control signal of the control circuit 1, and the signals generated under this control are synthesized by the synthesis circuit 4. What is converted into a serial signal becomes a continuous waveform as shown in FIG.

In this figure, an index frame M1, a test frame T1
．． It will be seen that the test signal is constructed in the order of the index frame M2 and the test frame T2.

FIG. 5 shows an example where the pattern shown in FIG. 3 changes due to non-uniform characteristics of the transmission system.

If an unfavorable condition occurs in the transmission system between the test signal generator and the receiver due to group delay frequency characteristics or other various characteristics, each test frame T , T , ...
・Test pattern t1. Since the frequency components of the signals t2°2, .

Here, since the frequency component of the index pulse m of the index frame M is always kept constant, it is possible to check whether the reproducibility of the received image is good or not based on the shaded portion m' of the index pulse m.

FIG. 6 is a diagram showing another example of signal coupling at the output of the test signal generator according to the present invention.

The index frames M1 and M2 include an identification code C in addition to the synchronization signal P and the index pulse m.

This identification code C is used when measuring by connecting a measuring device instead of a receiver.

That is, by identifying the start or end of the test signal or identifying the index frame M by the identification code C, measurement can be performed reliably.

In addition, the index pulse m may be used as a synchronization signal P or an identification code C before or after.
If the range is not affected by the unevenness of the transmission path, the index frame M1. The position of the index pulse m within M2, . . . may move within the index frame M.

The received image due to the index pulse m in Fig. 3 is a straight line, but as described above, the index pulse m within the index frame is changed as the frame progresses, and its relative position is changed so that the received image due to the index pulse m is The continuous figure can be other than a vertical line, such as a diagonal line.

Furthermore, the repetition of the index frame M and the test frame T does not have to be staggered.

For example, test frame T is used three times and index frame M is used once.
For example, the test frame T may be used once and the index frame M may be used three times.

FIG. 7 shows another example of a received image based on the test signal.

Of these, figure a shows a shape in which many patterns similar to the radial wedge pattern in figure 5, figure 3 a are gathered together with the same center.

Figure b is an enlarged view of portion b indicated by the chain line in figure a.

Further, Figure C is an enlarged view of the C portion indicated by the chain line in Figure A.

As is clear from the figure, the white signal and black signal in the test frames of FIGS. 7A and 7C are repeated alternately with the same width in the same row, and as the test frame T progresses, the It is configured to vary in width.

In this way, the test signal waveform in the test frame T can be made almost like a square wave, and compared to the example shown in Figure 3, which is close to a pulse wave, its contained frequency components can be made into a simple composition. can be in a state.

This makes it possible for the distortion of the received image to appear largely influenced by the frequency characteristics of the transmission system.

Furthermore, when a test signal is used in which the index pulse m and the test pattern t have the same rise and fall times, the influence of the frequency characteristics of the image transmission system may be difficult to appear on the received image.

This is because the frequency components of the index pulse m and the high frequency components related to the rising and falling times of the leading edge and trailing edge of the test pattern t, respectively, are similar.

Therefore, by making the rise and fall times of the index pulse m and test pattern t different so that their frequency components do not match, it is possible to make the frequency characteristics more likely to appear on the received image.

Specifically, in FIG. 2, this can be realized by providing both the index frame generation circuit 2 and the test frame generation circuit 30, or one of them, with a function of setting the rise and fall times.

In order to generate a plurality of test frames as shown in FIG. 7, for example, to explain with reference to the above-mentioned FIG. The circuit 32 gives digital counters 30 and 31 information representing the length of the test pulse in terms of the number of clock signals as the counter period, gives an output signal to the comparison circuits 33 and 34 for each period, and further sets the start point. Digital counters 30 and 3 from circuit 32
It is sufficient to give an initial count value to each of the above.

FIG. 8 is a block diagram showing another embodiment of the test signal generator according to the present invention, and shows an embodiment in which only the rise and fall times of the index pulse m are increased.

In the figure, a synchronization signal P is generated in a control circuit 1 and applied directly to a synthesis circuit 4.

The index frame generation circuit 2 and the test frame generation circuit 3 generate signals that do not include a synchronization signal.

A low-pass filter 8 is connected between the index frame generation circuit 2 and the synthesis circuit 4 for the purpose of blocking high frequency components of the index pulse m and increasing the rise and fall times.

FIG. 9 is an example of an output waveform diagram in the embodiment of FIG. 8.

As is clear from the figure, only the waveform of the index pulse m has long rise and fall times, and by transmitting such a waveform, the reception on the received image is greatly affected by the frequency characteristics of the image transmission system. Image distortion can be determined.

Note that in facsimile communication systems, it is generally considered unnecessary to consider interlaced scanning, but in television systems, it is a commonly used scanning system.

In the application of the present invention, it is difficult to evaluate the position of the screen where the synchronization signal interval changes due to interlaced scanning, but there is no problem if the central part of the screen that is not affected by this effect is used.

As explained in detail above, according to the present invention.

With a simple configuration, the reproducibility of the received image, which is affected by the characteristics of the image transmission system, can be easily determined on the received image, and there are also the following advantages.

(1) The influence of the frequency characteristics of a complex transmission system can be determined by a test signal generator that generates a simple geometric test pattern.

(2) Geometric patterns can be obtained by logical operations, so a large-capacity storage device is not required to generate one character, and many types of patterns can be realized with relatively simple circuits.

(3) Since it is sufficient to have a pattern according to the purpose, the number of types of patterns to be prepared can be reduced.

(4) Test charts require a long time in actual facsimile transmission because the test chart is sent and received in its entirety to evaluate its characteristics, but according to the present invention, the test signal is can be configured.

(5) Image distortion occurring in the received image can be visually checked using the line defined by the index pulse m as a reference without using a ruler or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a test signal generating device according to the present invention, FIG. 2 is a block diagram showing one embodiment of the device according to the present invention, and FIG. 2a is a specific example of an index frame generating circuit. FIG. 2b is a block diagram showing one specific example of the test frame generation circuit, FIG. 2c is a block diagram showing one specific example of the clock signal generation circuit, and FIG. 2d is a block diagram showing one specific example of the clock signal generation circuit.
The figure shows an example of the output waveform of the clock signal generation circuit of FIG. 2c, FIG. 3 shows an example of the relationship between the test signal and the pattern of the received image, and FIG. An example of the output waveform, Figure 5 is an example of a test pattern on the received image when it changes due to non-uniformity in the transmission system, Figure 6 is a diagram showing another example of the configuration of the test signal, Figure 7 is the test pattern Another example of a test pattern on a received image by a signal, FIG. 8 is a block diagram showing another embodiment of the device according to the present invention, and FIG. 9 is an example of an output waveform diagram in the embodiment of FIG. 8. be. In the figure, 1 is a control circuit, 2 is an index frame generation circuit, 3 is a test frame generation circuit, 4 is a synthesis circuit, 5 is a clock signal generation circuit, 6 is a carrier wave oscillation circuit, 7 is a modulation circuit, and 8 is a low-pass filter. .

Claims (1)

[Claims] 1. A test signal generation device characterized by temporally serially synthesizing an index frame of constant scan lines including an index pulse and a test frame of constant scan lines including a test pattern.