JPS58224561A - Switching type constant-voltage circuit - Google Patents

Switching type constant-voltage circuit

Info

Publication number
JPS58224561A
JPS58224561A JP10737682A JP10737682A JPS58224561A JP S58224561 A JPS58224561 A JP S58224561A JP 10737682 A JP10737682 A JP 10737682A JP 10737682 A JP10737682 A JP 10737682A JP S58224561 A JPS58224561 A JP S58224561A
Authority
JP
Japan
Prior art keywords
transistor
emitter
base
collector
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10737682A
Other languages
Japanese (ja)
Other versions
JPS6412178B2 (en
Inventor
Junzo Ono
小野 順造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP10737682A priority Critical patent/JPS58224561A/en
Publication of JPS58224561A publication Critical patent/JPS58224561A/en
Publication of JPS6412178B2 publication Critical patent/JPS6412178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To improve the efficiency of a constant-voltage circuit by maintaining the base current substantially constant to the variation in the input voltage of a transistor which performs switching operation. CONSTITUTION:The first transistor TR1 and a smoothing circuit 3 are connected in series between a DC power source 1 and a load 2. A reverse voltage absorbing diode D1 is connected between the first transistor TR1 and the smoothing circuit 3. The emitter of the third transistor TR3 is connected to the base of the first transistor TR1. A series circuit which has a resistor R6 and the second transistor TR2 is connected to the base of the third transistor TR3. The collector of the second transistor TR2 is connected to the connecting point 8 of a coil 6 and a capacitor 7. Since the base current of the first transistor TR1 flows through the emitter and the collector of the third transistor TR3 to the load 2, its efficiency is improved without waste.

Description

【発明の詳細な説明】 本発明はスイッチング式定電圧回路に関する。[Detailed description of the invention] The present invention relates to a switching type constant voltage circuit.

第1図を参照して、従来では、直流電源lと負荷2との
間に、第1トランジスタTRIと平滑回路3とが直列に
接続され、第1トランジスタTR1の動作を制御するだ
めの第2トランジスタTR2は制御パルス発生回路4に
よって制御される。
Referring to FIG. 1, conventionally, a first transistor TRI and a smoothing circuit 3 are connected in series between a DC power supply l and a load 2, and a second transistor TRI controls the operation of the first transistor TR1. Transistor TR2 is controlled by control pulse generation circuit 4.

このような従来技術において、第1トランジスタTRI
のベース電流iBが第2トランジスタTR2を流れるの
で、vJ1トランジスタTRIにおいてベース電流IB
が分流していることになり、効率が約80%程度に低下
する。
In such conventional technology, the first transistor TRI
Since the base current iB of flows through the second transistor TR2, the base current IB of vJ1 transistor TRI flows through the second transistor TR2.
is diverted, and the efficiency drops to about 80%.

このような分流電流IBを減少して効率を向上させるた
めには、第2図に示すように、第1トランジスタTRI
に第3トランジスタTR3をダーリントン接続すること
が単純には考えられる。この第2図の回路において、前
記ベース電流IBは、第3トランジスタTR3の電流増
幅率をhfeとすると、1/hf8だけ減少することに
なり、効率が向上するはずである。ところが、第3トラ
ンジスタTR3が制御パルス発生回路4からの制御パル
スに応じて導通ずると、第3トランジスタTR3のコレ
クタ・エミッタ電圧VCEはほぼ0■になる。これは、
第1トランジスタTRIにおいてはコレクタ電位VCと
ベース電位VBとがほぼ等しいということを意味する。
In order to reduce such shunt current IB and improve efficiency, as shown in FIG.
It is simply conceivable that the third transistor TR3 is connected in a Darlington manner. In the circuit of FIG. 2, the base current IB is reduced by 1/hf8, where hfe is the current amplification factor of the third transistor TR3, and the efficiency should be improved. However, when the third transistor TR3 becomes conductive in response to the control pulse from the control pulse generating circuit 4, the collector-emitter voltage VCE of the third transistor TR3 becomes approximately 0. this is,
This means that in the first transistor TRI, the collector potential VC and the base potential VB are approximately equal.

ここでエミッタ電位VEはVE=VB+0.8〜0.9
であるので、第1トランジスタTRIのコレクタ・エミ
ッタ間には0.8〜0.9■の電位差が伐ってしまうこ
とになる。したがって、第1トランジスタTRIにおけ
る損失が増大し、結果として効率は向上しない。
Here, the emitter potential VE is VE=VB+0.8 to 0.9
Therefore, a potential difference of 0.8 to 0.9 .mu. is created between the collector and emitter of the first transistor TRI. Therefore, the loss in the first transistor TRI increases, and as a result, the efficiency does not improve.

本発明は、上述の技術的課題を解決し、効率を向上させ
たスイッチング式電圧回路を提供することを目的とする
The present invention aims to solve the above-mentioned technical problems and provide a switching voltage circuit with improved efficiency.

以下、図面によって本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.

第3図は本発明の一実施例の電気回路図である。FIG. 3 is an electrical circuit diagram of one embodiment of the present invention.

直流電源1と負荷2との間には、第1トランジスタTR
Iと、平滑回路3とが直列に接続される。
A first transistor TR is connected between the DC power supply 1 and the load 2.
I and the smoothing circuit 3 are connected in series.

第1トランジスタTRIおよび平滑回路3間には逆電圧
吸収用ダイオードD1が接続される。また平滑回路3は
、コイル6およびコンデンサ7によって構成される。
A reverse voltage absorbing diode D1 is connected between the first transistor TRI and the smoothing circuit 3. Further, the smoothing circuit 3 includes a coil 6 and a capacitor 7.

第1トランジスタTRIはPNP )ランジスタであり
、この第1トランジスタTRIのベースには、PNPト
ランジスタである第3トランジスタTR3のエミッタが
接続される。第3トランジスタTR3のエミッタはまた
抵抗R1を介して第1トランジスタTRIのエミッタに
接続され、第3トランジスタTR3のベースは抵抗R1
,R2(i7介して第1トランジスタTRIのエミッタ
に接続される。さらに本発明に従えば、第3トランジス
タTR3のコレクタは、平滑回路3におけるコイル6お
よびコンデンサ7の接続点8に接続される。
The first transistor TRI is a PNP transistor, and the emitter of the third transistor TR3, which is a PNP transistor, is connected to the base of the first transistor TRI. The emitter of the third transistor TR3 is also connected to the emitter of the first transistor TRI via a resistor R1, and the base of the third transistor TR3 is connected to the emitter of the first transistor TRI through a resistor R1.
, R2 (connected to the emitter of the first transistor TRI via i7. Furthermore, according to the present invention, the collector of the third transistor TR3 is connected to the connection point 8 between the coil 6 and the capacitor 7 in the smoothing circuit 3.

平滑回路3および負荷2の接続点9には、抵抗R3、R
4、R5から成る直列回路が接続される。
At the connection point 9 between the smoothing circuit 3 and the load 2, resistors R3 and R
A series circuit consisting of 4 and R5 is connected.

抵抗R4には、その接続位置を自在にして制御パルス発
生回路4が接続される。したがって、制御パルス発生回
路4は、接続点9における電位に対応した電圧を検出し
、しかもその設定電圧を任意に変化させることができる
The control pulse generating circuit 4 is connected to the resistor R4 in a freely connected position. Therefore, the control pulse generation circuit 4 can detect the voltage corresponding to the potential at the connection point 9 and can arbitrarily change the set voltage.

第3トランジスタTR3のベースには、抵抗R6および
第2トランジスタTR2から成る直列回路が接続される
。′S2トランジスタ’I’R2は、NPNトランジス
タであシ、そのベースには制御パルス発生回路4からの
制御パルスが与えられる。
A series circuit consisting of a resistor R6 and a second transistor TR2 is connected to the base of the third transistor TR3. 'S2 transistor 'I'R2 is an NPN transistor, and a control pulse from control pulse generation circuit 4 is applied to its base.

上述のごとく第2トランジスタTR2のコレクタを、コ
イル6およびコンデンサ7の接続点8に接続することに
より、第3トランジスタTR3の導通時に第1トランジ
スタTRIのコレクタ電位VCよりも第3トランジスタ
TR3のコレクタ電位V’Cの方が低くなる。したがっ
て、前述の第2図で述べたように第1トランジスタTR
Iのエミッタ・コレクタ間に0.8〜0.9vの電位差
が伐ることがなく、第1トランジスタTRIの導通時に
エミッタ・コレクタ間の電位差はほぼ零になる。
As described above, by connecting the collector of the second transistor TR2 to the connection point 8 between the coil 6 and the capacitor 7, the collector potential of the third transistor TR3 is lower than the collector potential VC of the first transistor TRI when the third transistor TR3 is conductive. V'C becomes lower. Therefore, as described in FIG. 2 above, the first transistor TR
The potential difference of 0.8 to 0.9 V between the emitter and collector of I does not decrease, and the potential difference between the emitter and collector becomes almost zero when the first transistor TRI is conductive.

また第1トランジスタTRIのベース電流iBは第3ト
ランジスタTR3のエミッターコレクタを経て負荷2に
流れることになるので、無駄がなく、効率が向上する。
Furthermore, since the base current iB of the first transistor TRI flows to the load 2 via the emitter collector of the third transistor TR3, there is no waste and efficiency is improved.

第4図は本発明の他の実施例の電気回路図であり、第3
図の実施例に対応する部分には同一の参照符を付す。第
3図の実施例では、第1トランジ、2.りTR1のベー
ス電流i Bは、第1トランジスタTRIのベース・エ
ミッタ間電圧VBEおよび第3トランジスタTR3のベ
ース−エミッタl1flt圧V’BEによって定まる。
FIG. 4 is an electrical circuit diagram of another embodiment of the present invention;
Parts corresponding to the illustrated embodiments are given the same reference numerals. In the embodiment of FIG. 3, the first transition, 2. The base current iB of TR1 is determined by the base-emitter voltage VBE of the first transistor TRI and the base-emitter l1flt pressure V'BE of the third transistor TR3.

ところが副電圧VBE 。However, the sub voltage VBE.

VBEはダイオード特性を示すので、電流を適当な値に
設定することができない。そこで、この実施例では、コ
イル6にタップを設けて、第3トランジスタTR3のコ
レクタをコイル6に接続する。
Since VBE exhibits diode characteristics, the current cannot be set to an appropriate value. Therefore, in this embodiment, a tap is provided in the coil 6, and the collector of the third transistor TR3 is connected to the coil 6.

このようにすればベース電流IBを適当な値に設定する
ことができる。ようになる。
In this way, the base current IB can be set to an appropriate value. It becomes like this.

また、v;5図で示すように、ベース電流IBを適当な
値に設定するために、第3トランジスタTR3のコレク
タを抵抗R7を介して接続点8に接続するようにしても
よい。
Furthermore, as shown in FIG.

第6図は本発明の他の実施例の電気回路図であり、前述
の各実施例に対応する部分には同一の参照符を付す。こ
の実施例では、第1トランジスタTRIのベース電流I
Bを定電流化して効率をさらに向上するために、第1ト
ランジスタTRIのベースおよび第3トランジスタTR
3のエミッタ間に抵抗R8を介在させる。これによって
、第1トランジスタTRIの入力電圧Eの変化に対応し
た広い電圧変化に対してペース電流iBがほぼ一定とな
り、効率が同一ヒする。
FIG. 6 is an electrical circuit diagram of another embodiment of the present invention, and parts corresponding to each of the embodiments described above are given the same reference numerals. In this embodiment, the base current I of the first transistor TRI
In order to make B a constant current and further improve efficiency, the base of the first transistor TRI and the third transistor TR
A resistor R8 is interposed between the emitters of 3 and 3. As a result, the pace current iB becomes substantially constant over a wide range of voltage changes corresponding to changes in the input voltage E of the first transistor TRI, and the efficiency remains the same.

第7図は本発明の他の実施例の電気回路図であり、前述
の各実施例に対応する部分には同一の参照符を付す。こ
の実施例では、抵抗R2と並列に少なくとも1個望まし
くは2個のダイオードD2゜D3が接続される。このよ
うにすると、抵抗R2の両端の電圧が定電圧化され、第
3トランジスタTR3のコレクタ電流が定電流化される
ので、効率が向上する。
FIG. 7 is an electrical circuit diagram of another embodiment of the present invention, and parts corresponding to each of the embodiments described above are given the same reference numerals. In this embodiment, at least one and preferably two diodes D2 and D3 are connected in parallel with the resistor R2. In this way, the voltage across the resistor R2 is made constant, and the collector current of the third transistor TR3 is made constant, thereby improving efficiency.

また、第8図で示すように、抵抗R2と並列に、ダイオ
ードD4および抵抗 4.4.6成60列、あを接続し
てもよく、さらに第9図で示すように、抵抗R2と並列
にツェナダイオードZDを接続してもよい。
In addition, as shown in FIG. 8, a diode D4 and a resistor (4.4.6, 60 series, A) may be connected in parallel with the resistor R2, and further in parallel with the resistor R2, as shown in FIG. A Zener diode ZD may be connected to the zener diode ZD.

上述のごとく本発明によれば、第3トランジスタのコレ
クタをタップが設けられたコイルあるいはコイルおよび
負荷間に接続するようにしたので、第1トランジスタに
おけるコレクタ損失が減少し、しだがって効率が向上す
る。
As described above, according to the present invention, since the collector of the third transistor is connected to the tapped coil or between the coil and the load, the collector loss in the first transistor is reduced, and therefore the efficiency is improved. improves.

【図面の簡単な説明】[Brief explanation of drawings]

′141図は在米技術を示す電気回路図、第2図は在米
技術の欠点を解消するために単純に思い付く電気回路図
、第3図は本発明の一実施例の電気回路図、第4図、第
5図、第6図、第7図、第8図および第9図は本発明の
他の実施例をそれぞれ示す電気回路図である。 1・・・直流電源、2・・・負荷、3・・・平滑回路、
4・・・制御パルス発生回路、6・・コイル、TRI・
・・第1トランジスタ、TR2・・・%2トランジスタ
、TR3・・・第3トランジスタ 代理人   弁理士 西教圭一部 第1図 第2図 第3図 特開昭58−224561(4)
Figure 141 is an electrical circuit diagram showing the American technology, Figure 2 is an electrical circuit diagram simply conceived to eliminate the drawbacks of the American technology, and Figure 3 is an electrical circuit diagram of an embodiment of the present invention. 4, 5, 6, 7, 8 and 9 are electrical circuit diagrams showing other embodiments of the present invention, respectively. 1... DC power supply, 2... Load, 3... Smoothing circuit,
4... Control pulse generation circuit, 6... Coil, TRI.
...1st transistor, TR2...%2 transistor, TR3...3rd transistor Agent Patent Attorney Kei Nishi Part 1 Figure 2 Figure 3 JP-A-58-224561 (4)

Claims (1)

【特許請求の範囲】[Claims] 直流電源と負荷との聞に、スイッチング動作を果す第1
トランジスタと、コイルを含む平滑回路とを直列に接続
し、第1トランジスタのスイッチング動作を制御する第
2トランジスタを、前記負荷に与えられる電圧に対応し
て制御パルスを発生する制御パルス発生回路によって制
御するようにしたスイッチング式定電圧回路において、
第1トランジスタのベースを第3トランジスタのエミッ
タに接続するとともに、第3トランジスタのエミッタと
第1トランジスタのエミッタと・を抵抗を介して接続し
、さらに第3トランジスタのベースを他の抵抗を介して
第1トランジスタのエミッタに接続するとともに第2ト
ランジスタに接続し、第3トランジスタのコレクタを、
タップが設けられたコイルあるいはコイルおよび負荷間
に接続することを特徴とするスイッチング式定電圧回路
Between the DC power supply and the load, there is a first
A transistor and a smoothing circuit including a coil are connected in series, and a second transistor that controls the switching operation of the first transistor is controlled by a control pulse generation circuit that generates a control pulse in response to a voltage applied to the load. In a switching type constant voltage circuit designed to
The base of the first transistor is connected to the emitter of the third transistor, the emitter of the third transistor and the emitter of the first transistor are connected via a resistor, and the base of the third transistor is connected via another resistor. connected to the emitter of the first transistor and connected to the second transistor, and the collector of the third transistor;
A switching type constant voltage circuit characterized by being connected between a coil provided with a tap or a coil and a load.
JP10737682A 1982-06-21 1982-06-21 Switching type constant-voltage circuit Granted JPS58224561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10737682A JPS58224561A (en) 1982-06-21 1982-06-21 Switching type constant-voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10737682A JPS58224561A (en) 1982-06-21 1982-06-21 Switching type constant-voltage circuit

Publications (2)

Publication Number Publication Date
JPS58224561A true JPS58224561A (en) 1983-12-26
JPS6412178B2 JPS6412178B2 (en) 1989-02-28

Family

ID=14457532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10737682A Granted JPS58224561A (en) 1982-06-21 1982-06-21 Switching type constant-voltage circuit

Country Status (1)

Country Link
JP (1) JPS58224561A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617286U (en) * 1984-06-14 1986-01-17 富士電機株式会社 DC-DC converter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS579302A (en) * 1980-06-18 1982-01-18 Hitachi Constr Mach Co Ltd Unload valve

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS579302A (en) * 1980-06-18 1982-01-18 Hitachi Constr Mach Co Ltd Unload valve

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617286U (en) * 1984-06-14 1986-01-17 富士電機株式会社 DC-DC converter

Also Published As

Publication number Publication date
JPS6412178B2 (en) 1989-02-28

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