JPS6149521A - Switch circuit - Google Patents

Switch circuit

Info

Publication number
JPS6149521A
JPS6149521A JP59172010A JP17201084A JPS6149521A JP S6149521 A JPS6149521 A JP S6149521A JP 59172010 A JP59172010 A JP 59172010A JP 17201084 A JP17201084 A JP 17201084A JP S6149521 A JPS6149521 A JP S6149521A
Authority
JP
Japan
Prior art keywords
resistor
npn transistor
diode
base
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59172010A
Other languages
Japanese (ja)
Inventor
Harunori Sato
里　治則
Ryuichi Sakano
坂野　竜一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59172010A priority Critical patent/JPS6149521A/en
Publication of JPS6149521A publication Critical patent/JPS6149521A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
    • H03K17/0422—Anti-saturation measures

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent a switching transistor (TR) from being saturated after turning on and put a trailing-stage circuit in operation speedily by providing a circuit which generates a constant voltage for the TR. CONSTITUTION:One terminal of a resistor R1 is connected to the input voltage Vin of a switching circuit and the other terminal T0 of the resistor R1 is branched into two. The 1st and the 2nd diodes D1 and D2 are connected in series with one cable way and the base of a switching NPNTRQ1 is connected to a diode D2. Further, the other branched cable way connects with the collector of an NPNTQ2 and one terminal of a resistor R4, a resistor R3 is connected to the connection point between the base of the TRQ2 and resistor R4, and the connection point is connected to the emitter of the TRQ2. Further, a diode D3 which prevents a reverse current when the TRQ1 is off is connected between the TRs Q1 and Q2. Then, the constant voltage is generated by the TRQ2 and resistors R3 and R4 to prevent saturation when the TRQ1 turns on, speeding up the operation of the circuit connected to an output terminal T.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、高速動作でＴＴＬＹ直接駆動可能にしたス
イッチ回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a switch circuit that operates at high speed and is capable of directly driving TTLY.

〔従来技術〕[Prior art]

第１図は従来の高速スイッチ回路を示すものである。　
　　　　　′ 第１図において、■１は電源を示す入力電圧、Ｒ＋、Ｒ
２は第１．第２の抵抗体（以下、第１゜第２．・・・・
・・は省略し単に抵抗体という。他の符号についても同
様とする。ま７ｊ、　Ｒ＋　ｒ　　Ｒ２＋　・・・・・
・はその抵抗値をも表わ丁。）、Ｑ、はスイッチ用のＮ
ＰＮ　トランジスタ、ｖｃｃは電源電圧、■は出力端子
である。FIG. 1 shows a conventional high-speed switch circuit.
' In Figure 1, ■1 is the input voltage indicating the power supply, R+, R
2 is the first. Second resistor (hereinafter referred to as 1st, 2nd...
... is omitted and is simply referred to as a resistor. The same applies to other symbols. Ma7j, R+ r R2+...
・also represents its resistance value. ), Q, is N for the switch
PN transistor, vcc is the power supply voltage, and ■ is the output terminal.

次に動作について説明する。Next, the operation will be explained.

第１図忙おい箋、入力電圧Ｖ１＝Ｖ、が印加さｎると、
ＮＰＮトランジスタＱ＋のパシ弓１←ゆベースＶＣはベ
ース電流ＩＢｌが流ｎ、 トｔｘ　ル（７，：　ｒ　Ｌ、■＋　＞　Ｖｍｇ＋　ａ
　Ｖｍｚ＋　４’：ＣＮ　Ｐ　Ｎ　トランジスタＱ、の
ベース・エミッタ順方向電圧である）。Fig. 1 busy note, when input voltage V1=V is applied,
The base current IBL flows through the NPN transistor Q+'s passive bow 1←base VC.
Vmz+4': Base-emitter forward voltage of CN P N transistor Q).

また、ベース電流Ｉｌｌが次の第（２）式ン満丁時、Ｎ
ＰＮトランジスタＱ、は導通し”ＯＮ”となる。In addition, when the base current Ill is full according to the following equation (2), N
The PN transistor Q becomes conductive and becomes "ON".

にｇし、ｈ□、はＮＰＮトランジスタＱ、の電離増幅率
、■ｃＥ８、はコレクタ・エミッタ間の飽和電圧である
。, h□ is the ionization amplification factor of the NPN transistor Q, and cE8 is the saturation voltage between the collector and emitter.

この時、出力端子Ｔの電圧■Ｔ　は ｖＴ　”ＶＣ１！８１　　　・・・・・・・・・・・・
・・・・・・−・・・・−・（３）となる。At this time, the voltage ■T of the output terminal T is vT ”VC1!81 ・・・・・・・・・・・・
・・・・・・－・・・・・・－・(3)

次に、入力電圧ｖ１１に〇の時、ベース電流ＩＢ＋二〇
となり、ＮＰＮ　トランジスタＱ、はカットオフとなり
、 ｖＴ　＝ｖｏｃ　　　・・・・・・・・・・・・・・・
・・　・・・・・・・・・（４）となり、入力電圧ｖＩ
１１の大きさに応じてＮＰＮトランジスタＱ、は０Ｎ１
０ＦＦのスイッチ動作ケする。Next, when the input voltage v11 is 0, the base current IB + 20, the NPN transistor Q is cut off, and vT = voc ・・・・・・・・・・・・・・・
・・・・・・・・・(4) becomes, and the input voltage vI
Depending on the size of 11, the NPN transistor Q, is 0N1
Operate the 0FF switch.

従来の回路において、前記第（２）式を満に丁“ＯＮ”
状態のとき、ＮＰＮトランジスタＱ、は飽和する。この
為、ＮＰＮトランジスタＱ＋　のベース内で多数キャリ
アが残る為、入力電圧Ｖ、、＝ＯとなってＮＰＮトラン
ジスタＱ、がＯＦＦ″”に反転する時、前記多数キャリ
ア？再結合するのに必要な時間は長（、この時間が遅ｆ
時間の太半乞占め、高速動作が必要とさｎるときは性能
上達成できないというような欠点があった。In the conventional circuit, the above equation (2) is completely “ON”.
In this state, the NPN transistor Q is saturated. For this reason, majority carriers remain in the base of the NPN transistor Q+, so when the input voltage V, , = O and the NPN transistor Q is inverted to OFF, the majority carriers? The time required to recombine is long (, this time is slow f
The disadvantages are that it takes up a lot of time, and when high-speed operation is required, it cannot be achieved in terms of performance.

〔発明の概要〕[Summary of the invention]

この発明は、上記のような従来のものの欠点を除去する
為になさｎたもので、ＮＰＮ　トランジスタがＯＮ”の
時に飽和しないようにしにスイッチ回路ヶ提供するもの
である。以下、この発明の一実施例を図面乞用いて説明
する。This invention was made to eliminate the drawbacks of the conventional ones as described above, and provides a switch circuit to prevent the NPN transistor from being saturated when it is ON. An embodiment will be described with reference to the drawings.

〔発明の実施例〕[Embodiments of the invention]

第２図はこの発明の一実施例を示す回路図であ゛る。 FIG. 2 is a circuit diagram showing one embodiment of the present invention.

第２図において、ＤＩ、Ｄ２は前記ＮＰＮトランジスタ
Ｑ、のベースに直列に接続さ７’Ｌ　ｆ、−タイオード
である。また、ダイオードＤ１　の１ノードと抵抗体８
１０間の端子′Ｉ！：Ｔｏ　として、この端子Ｔ。In FIG. 2, DI, D2 is a 7'L f,-diode connected in series with the base of the NPN transistor Q. In addition, one node of the diode D1 and the resistor 8
Terminal 'I! between 10! :To as this terminal T.

より電路を２つに分岐し、その一方の電路に前述したダ
イオードＤ　＋　、Ｄｚ、’ｒ　２測置列に接続し、そ
の先端のダイオードＤ２のカソードをスイッチ用のＮＰ
、ＮトランジスタＱ、のベースに接続し、また、分岐し
た電路の他方にけＮＰＮ　トランジスタＱ２のコレクタ
と抵抗体Ｒ４の一端に接続さｎ、ＮＰＮトランジスタＱ
２のベースと抵抗体Ｒ，の他端と抵抗体Ｒ８の一端が接
続さｎ、ＮＰＮトランジスタＱ２のエミッタと抵抗体Ｒ
ｓの他端とダイオードＤ、のアノードが接続さｒｌ、ダ
イオードＤ３のカソードはＮＰＮトランジスタＱ、のコ
レクタに接続さｊｌている。このタイオードＤ３はＮＰ
ＮトランジスタＱ１が”　ＯＦ　Ｆ　”時の回り込み防
止用のダイオードで、ＮＰＮ　トランジスタＱ２゜抵抗
体Ｒｓ、Ｒａは定電圧を発生させる為のものである。The electric path is branched into two, and one of the electric paths is connected to the aforementioned diode D
, N is connected to the base of the NPN transistor Q, and is connected to the collector of the NPN transistor Q2 and one end of the resistor R4 on the other side of the branched electric path.
The base of the transistor Q2 is connected to the resistor R, the other end is connected to one end of the resistor R8, and the emitter of the NPN transistor Q2 is connected to the resistor R.
The other end of s is connected to the anode of diode D, rl, and the cathode of diode D3 is connected to the collector of NPN transistor Q, jl. This diode D3 is NP
The NPN transistor Q2 is a diode for preventing loop current when it is "OFF", and the resistors Rs and Ra of the NPN transistor Q2 are used to generate a constant voltage.

第３図、第４図は第２図の動作説明図であり、以下第３
図、第４図を用いて第２図の動作ケ説明する。3 and 4 are explanatory diagrams of the operation of FIG.
The operation of FIG. 2 will be explained using FIGS.

第２図において、入力電圧Ｖい＝ＶＢが印加さｎると、
ＮＰＮトランジスタＱ＋＜流ｎるベースｌＩＬ流より□
は である。ｒｓ　ｒ　Ｌ、Ｖｏｗ　＋　　Ｖａ２に’ｆ：
、　ｆ　イｔ　−）−Ｃ＋　＋Ｄ２の順方向電圧である
。この時、ＮＰＮトランジスタＱ、のコレクタ・エミッ
タ間の電圧ＶＴ　’？：約０．４〜０．５ｖ程度に設定
すると、導通時でも一非飽和で高速動作させることがで
きる。ここで、ＮＰＮトランジスタＱ、のベース電流■
Ｂ３はとなり、ＮＰＮ　トランジスタＱ２＋　　ダイオ
ードＤ３に流ｎる電流ＩＢ４は ＩＢ４　”　ｌｌ１２　　ＩＢｇ　　　・・・・・・・
・・・・・・・・・・・・・（７）となり、ＮＰＮトラ
ンジスタＱ２のコレクタ・エミッタ間電圧ｖｃＥ２　　
は となる。Ｌｘし、ＮＰＮトランジスタＱ２の電流増幅率
ｔｌｆｅ２は、ｈｇｅｔ　＞　１で、ペース電流は無視
できるものとする。この時、抵抗体Ｈ３，Ｒ４に流ｆる
電流■Ｒは となり、ＮＰＮトランジスタＱ２のフレフタ電流ＩＣ２
は・ ＩＣ２”　ＩＲ４ＩＲ ・・・・・・・・・・・・（１０） となる。In Fig. 2, when input voltage V=VB is applied,
NPN transistor Q+<flow n base lIL flow□
It is. rs r L, Vow + Va2 'f:
, f is the forward voltage of −)−C+ +D2. At this time, the voltage VT' between the collector and emitter of the NPN transistor Q? : When set to about 0.4 to 0.5 V, high-speed operation can be achieved with one non-saturation even when conducting. Here, the base current of the NPN transistor Q,
B3 becomes, and the current IB4 flowing through the NPN transistor Q2+ diode D3 is IB4 '' ll12 IBg ......
・・・・・・・・・・・・(7), and the collector-emitter voltage vcE2 of the NPN transistor Q2
Hato becomes. It is assumed that the current amplification factor tlfe2 of the NPN transistor Q2 is hget > 1, and the pace current can be ignored. At this time, the current f flowing through the resistors H3 and R4 becomes
is IC2” IR4IR (10).

次に゛第３図を用いて、瑞子Ｔ、−Ｔ間に発生する電圧
の説明乞する。Next, with reference to FIG. 3, I would like to explain the voltage generated between Mizuko T and -T.

曲線（Ａ）はダイオードＤ３の順方向特性、曲線（Ｂ）
はＮＰＮトランジスタＱ、のコレクタ・エミッタ間電圧
Ｖｃ、２　の順方向特性１曲線（Ａ＋Ｂ）はＮＰＮトラ
ンジスタＱ零、ダイオードＤ３が直列接続さｎ、、ｒｓ
状態の順方向特性であり、前記第（社）ン式で求め７ｊ
Ｉｃｉが、Ｉｃｉ＞Ｉｃｅの時、ＮＰＮトランジスタＱ
２、ダイオード０３は定電圧領域に入つており、その電
圧ｖＴ−Ｔｏは、 となり、動作点はＰ、　　Ｋ位置する。なお、Ｉｃｅは
第３図における定電圧領域における最小コレクタ電流を
示す。Curve (A) is the forward characteristic of diode D3, curve (B)
is the collector-emitter voltage Vc of the NPN transistor Q, 2, and the forward characteristic curve (A+B) of the NPN transistor Q0 and the diode D3 are connected in series n,,rs
It is the forward characteristic of the state, and is calculated using the above formula 7j
When Ici is Ici>Ice, the NPN transistor Q
2. The diode 03 is in the constant voltage region, the voltage vT-To is as follows, and the operating points are located at P and K. Note that Ice indicates the minimum collector current in the constant voltage region in FIG.

第４図乞用いて出力電圧ｖＴ乞求める。第２図の端子Ｔ
。の電圧はＶＴｏユ３ｖＢ、２となり、その電位より第
（１１）式で求め７ＣＶ　Ｔ−Ｔ　１１の電位だけ低く
なり、 ＶＴ　＝Ｖ、Ｏ−Ｖ丁−，。Determine the output voltage vT using Figure 4. Terminal T in Figure 2
. The voltage of VTo is 3vB,2, which is calculated by equation (11) and is lower by the potential of 7CV T-T11, VT = V, O-V-,.

となる。動作点は１／Ｒ２で示す破線との交点Ｐ２とな
る。becomes. The operating point is the intersection point P2 with the broken line indicated by 1/R2.

ココテ、Ｖ　５ｇ２　”　７００　ｍ　Ｖｅ　Ｒｓ　”
　４　ＫΩ、Ｒ４＝１０にΩに選ぶとき、第（１２）式
に代入してｖＴよ４２０ｍＶとなり、次段のＴＴＬｖ”
ＯＦＦ″にすることは可能である。Cocote, V5g2 ”700m Ve Rs”
When selecting 4 KΩ, R4 = 10Ω, substituting it into equation (12), vT becomes 420mV, and the TTLv of the next stage is
It is possible to turn it off.

次に、第２図においてｖＩｎ＝０が印加さｎると、ＮＰ
ＮトランジスタＱ、はオフとなる。次段のＴＴＬＹ″Ｏ
Ｎ″にすることは可能でスイッチ回路として充分な動作
をする。Next, in FIG. 2, when vIn=0 is applied, NP
N transistor Q is turned off. Next stage TTLY″O
It is possible to set the value to N'', and it operates satisfactorily as a switch circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明Ｌ　７Ｃよ５Ｖｃ、この発明は、第１の抵抗体
の一端を入力電圧に接続し、この第１の抵抗体の他端よ
り電路を２つに分岐し、その一方の電路に第１．第２の
ダイオードを直列接続してその端部Ｚスイッチ用の第１
のＮＰｌｊトランジスタのベース忙接続し、この第１の
ＮＰＮトランジスタのエミッタを接地し、また、前記分
岐し定電路の他端は第２のＮＰＮトランジスタのコレク
タと第４の抵抗体の一端ＶＣ接続し、前記第２のＮＰＮ
トランジスタのベースと第４の抵抗体の他端に第３の抵
抗体の一端を接続し、前記第２のＮＰＮトランジスタの
エミッタと第３の抵抗体の他端と第３のダイオードのア
ノードを接続し、前記第３のダイオードのカソードと、
第１のＮＰＮ　トランジスタのコレクタと第２の抵抗体
の一端を接続し、この第２の抵抗体の他端と電源端子を
接続しているので、次段でＴＴＬｙ！ｌ−駆動させると
き高速動作させることができ、民生用、産業用の分野に
幅広（用いることができる。まＬ、集積回路に構成する
とき、ショットギトランジスタが不要となるので、安価
な標準プロセスにより、高速のスイッチ回路第１図は従
来のスイッチ回路図、第２図はこの乞ａ成できる利点が
ある。The above explanation L7C5Vc, this invention connects one end of the first resistor to the input voltage, branches the electric path into two from the other end of the first resistor, and connects the first electric path to one of the electric paths. ．． A second diode is connected in series with the first one for the Z switch at its end.
The base of the NPN transistor is connected to the base of the first NPN transistor, the emitter of the first NPN transistor is grounded, and the other end of the branched constant current path is connected to the collector of the second NPN transistor and one end of the fourth resistor to VC. , said second NPN
One end of a third resistor is connected to the base of the transistor and the other end of the fourth resistor, and the emitter of the second NPN transistor and the other end of the third resistor are connected to the anode of the third diode. and a cathode of the third diode;
Since the collector of the first NPN transistor and one end of the second resistor are connected, and the other end of this second resistor is connected to the power supply terminal, the TTLy! It can operate at high speed when driven, and can be used in a wide range of consumer and industrial fields.Also, when configured into an integrated circuit, Schottky transistors are not required, making it an inexpensive standard process. Therefore, the high-speed switch circuit shown in FIG. 1 has the advantage of being a conventional switch circuit, whereas the switch circuit shown in FIG.

【図面の簡単な説明】[Brief explanation of drawings]

発明の一実施例によるスイッチ回路、第３図、第４図は
第２図の動作説明のための特性曲線図である。 図中、Ｒ，−Ｒ，ｔ２抵抗体、ｖ、ｆｉｉｔ入力電圧、
　　　　　　　　　、Ｑ、、Ｑ、はＮＰＮトランジスタ
、０１〜Ｄ３はダイオードである。 なお、図中の同一符号は同一まｙ：は相当部分を示す。 代理人　大岩　増　雄　　　（外２名）第１図 第３図 第４図 ｃｃｍ １、事件の表示　　　特願昭５９−．１７２０１０号２
、発明の名称　　　スイッチ回路 ３、補正をする者 ５、補正の対象 図面 ６、補正の内容 第３図を別紙のように補正する。 以　　上FIGS. 3 and 4 are characteristic curve diagrams for explaining the operation of the switch circuit according to an embodiment of the invention in FIG. 2. In the figure, R, -R, t2 resistor, v, fiit input voltage,
, Q, ,Q are NPN transistors, and 01 to D3 are diodes. Note that the same reference numerals in the figures indicate the same parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 3 Figure 4 ccm 1. Indication of the case Patent application 1984-. 172010 No. 2
, title of the invention Switch circuit 3, person making the amendment 5, drawing to be amended 6, contents of the amendment Figure 3 will be amended as shown in the attached sheet. that's all

Claims (1)

【特許請求の範囲】[Claims] 第１の抵抗体の一端を入力電圧に接続し、この抵抗体の
他端より電路を２つに分岐し、その一方の電路に第１、
第２のダイオードを直列接続してその端部をスイッチ用
の第１のＮＰＮトランジスタのベースに接続し、この第
１のＮＰＮトランジスタのエミッタを接地し、また、前
記分岐した他方の電路に第２のＮＰＮトランジスタのコ
レクタと第４の抵抗体の一端を接続し、前記第２のＮＰ
Ｎトランジスタのベースと前記第４の抵抗体の他端に第
３の抵抗体の一端を接続し、前記第２のＮＰＮトランジ
スタのエミッタと前記第３の抵抗体の他端と第３のダイ
オードのアノードを接続し、この第３のダイオードのカ
ソードと、第１のＮＰＮトランジスタのコレクタと第２
の抵抗体の一端を接続し、さらに前記第２の抵抗体の他
端を電源端子に接続したことを特徴とするスイッチ回路
。One end of the first resistor is connected to the input voltage, an electric path is branched into two from the other end of the resistor, and one of the electric paths has a first
A second diode is connected in series, the end thereof is connected to the base of the first NPN transistor for switching, the emitter of this first NPN transistor is grounded, and a second diode is connected to the other branched electric path. The collector of the NPN transistor is connected to one end of the fourth resistor, and the collector of the second NPN transistor is connected to one end of the fourth resistor.
One end of a third resistor is connected to the base of the NPN transistor and the other end of the fourth resistor, and the emitter of the second NPN transistor and the other end of the third resistor are connected to the other end of the third diode. The anode of the third diode is connected to the collector of the first NPN transistor and the cathode of the third diode.
A switch circuit characterized in that one end of the second resistor is connected to the second resistor, and the other end of the second resistor is connected to a power supply terminal.
JP59172010A 1984-08-17 1984-08-17 Switch circuit Pending JPS6149521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59172010A JPS6149521A (en) 1984-08-17 1984-08-17 Switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59172010A JPS6149521A (en) 1984-08-17 1984-08-17 Switch circuit

Publications (1)

Publication Number Publication Date
JPS6149521A true JPS6149521A (en) 1986-03-11

Family

ID=15933849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59172010A Pending JPS6149521A (en) 1984-08-17 1984-08-17 Switch circuit

Country Status (1)

Country Link
JP (1) JPS6149521A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277306U (en) * 1988-12-01 1990-06-13
US5481216A (en) * 1994-05-31 1996-01-02 National Semiconductor Corporation Transistor drive circuit with shunt transistor saturation control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277306U (en) * 1988-12-01 1990-06-13
US5481216A (en) * 1994-05-31 1996-01-02 National Semiconductor Corporation Transistor drive circuit with shunt transistor saturation control

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