JPH06152360A - Switching circuit with clamping function - Google Patents

Abstract

PURPOSE:To provide a switching circuit having a clampling function which is appropriate for integration without constituting a parasitic element. CONSTITUTION:The switching circuit is constituted of the 1st transistor (TR) Q2 connecting its collector to a power supply V+ through a diode D1 and a resistor R1 and connecting its emitter to a reference potential (V-) through a resistor R2 so as to be driven by an input signal (Vin), the 2nd TR Q1 connecting its base, emitter and collector respectively to the anode of the diode D1, the power supply V+ and an output terminal Vo and the 3rd TR Q3 connecting its base, emitter and collector respectively to the collector of the TR Q2, the collector of the TR Q1 and the emitter of the TR Q2 so as to be controlled at its drive by the collector potential of the TR Q2, branch a prescribed current from an output current and allow the branched current to flow into the reference potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit having a clamp function for controlling an output voltage to a predetermined value.

[0002]

2. Description of the Related Art FIG. 2 shows a switch circuit using a conventional PNP transistor. In this switch circuit, a transistor Q driven by an input signal (Vin)
2 collector is connected to power supply V + via resistor R1,
The emitter is connected to the reference potential (V-) through the resistor R2, the base of the transistor Q1 is connected to the collector of the transistor Q2, the emitter is connected to the power supply V +, and the collector is connected to the output terminal Vo. Is provided and configured.

In such a switch circuit, the potential Vin of the input signal is set to a level such that the transistor Q2 is turned on when the potential Vin is "High" and the transistor Q2 is completely cut off when the potential Vin is "Low". There is.
Here, when the input potential Vin is "High", a current as shown in the following equation flows through the transistor Q2.

[0004]

[Equation 1]

A part of this current flows from the power source V + through the resistor R1, and the rest of the current flows through the transistor Q.
It becomes a base current of 1. Here, the transistor Q1
The output current Iout is β × I
_{When the} load is _B1 but the load connected to the output voltage terminal Vo is large, the potential of the output potential Vout approaches V +, and the transistor Q1 becomes saturated. In this case,
The increase in the base current I _B1 reduces the apparent β of the transistor Q1. Particularly in the case of an integrated circuit, the parasitic transistor begins to operate and a current flows in the substrate.

On the other hand, when the input potential Vin is "Low",
Since the transistor Q1 is cut off, the base potential of the transistor Q1 becomes V + and the transistor Q1 is cut off. Therefore, the output voltage terminal Vo
Becomes an open state and has a potential determined by the connected load.

As described above, the potential of the output changes from "High" (approximately V +) to "Lo" depending on the potential Vin of the input signal.
w "(potential determined by the load), and the transistor Q1 operates as if it were a switch element.

However, as described above, when the transistor Q1 is saturated, a current flows in the substrate, which may adversely affect other devices depending on its level.
Further saturation causes the transistor Q1
There is also a problem in that the off-speed of the transistor Q1 becomes slow due to excess charges accumulated in the base region of the transistor Q1.

Therefore, the above-mentioned problem has been solved by using a switch circuit as shown in FIG. In this switch circuit, a diode D1 made of a transistor is added between the base of the transistor Q1 and the collector of the transistor Q2, and a diode D2 made of a transistor is added between the collector of the transistor Q1 and the collector of the transistor Q2 in the circuit configuration shown in FIG. Circuit.

In this configuration, the transistor Q
When 2 turns on and a current flows, the collector potential of the transistor Q1, that is, the output potential starts to rise,
This potential

[0011]

[Equation 2] At that time, the feedback current Ic4 starts to flow, and eventually the output potential Vout is fixed to the value obtained by the equation (2), and the transistor Q1 does not saturate. Further, the relation of each current when the transistor Q2 is turned on is as follows.

[0012]

[Equation 3] Therefore,

[0013]

[Equation 4] Is obtained. Here, assuming that β is sufficiently larger than 1, equation (3) becomes

[0014]

[Equation 5] Becomes

[0015]

However, although the above-mentioned switch circuit has a structure which has been generally used as a clamp circuit in the past, an integrated circuit (I
When adopted in C) and incorporated in a laminated structure, the following problems occur.

First, the diode D2 shown in FIG.
In the case of the NPN transistor as shown in (a), when the transistor Q2 is turned off, the collector potential Vc of the transistor Q2 rises. At this time, if the potential of the output potential Vout is low, the reverse bias applied to the diode D2 becomes large, and breakdown may occur between the emitter-base junction of the transistor, which may cause malfunction.

Further, when the diode D2 is composed of a PNP transistor as shown in FIG. 4B, when the transistor Q2 is turned off, the collector potential Vc of the transistor Q2 rises. As in the case of the NPN transistor, when the output potential Vout is low, the reverse bias applied to the diode D2 becomes large. At this time,
The collector potential of the transistor used as the diode D2 becomes higher than the emitter potential, but in some cases, the emitter electrode functions as a gate, and a PMOS using the emitter and collector as sources and drains may be configured and operated, resulting in malfunction. Can cause. Therefore, an object of the present invention is to provide a switch circuit having a clamp function, which is suitable for integration without forming a parasitic element.

[0018]

In order to achieve the above object, the present invention is driven by an input signal, a collector is connected to a power source through a diode and a first resistor, and an emitter is connected through a second resistor. A first transistor connected to a reference potential and a base connected to the anode of the diode, which outputs a predetermined potential or is switched to an open state in response to the driving of the first transistor. Of the first transistor and the collector of the first transistor are connected to the base, the collector of the second transistor is connected to the emitter, the emitter of the first transistor is connected to the collector, and the first transistor is turned on. Occasionally, a third transistor for controlling the collector-side potential of the second transistor to a constant potential is used. To provide a function switch circuit.

[0019]

In the switch circuit configured as described above, when the first transistor is turned on, the collector potential of the second transistor tries to rise, but when the third transistor is turned on, a current starts to flow in the emitter. , Through the collector to the emitter of the first transistor. Also, when the first transistor is turned off,
Since the collector potential of the third transistor is always the minimum potential, the potentials of the collector and the emitter do not reverse and no malfunction occurs due to the parasitic PMOS.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a switch circuit as an embodiment according to the present invention, which will be described. In this switch circuit, a transistor Q2 driven by an input signal (Vin) has a collector connected to the cathode of a diode D1 and an emitter connected via a resistor R2 to a reference potential (V-).
Connected to. The anode of the diode D1 has a resistance R
1 to the power supply V +. The base of the transistor Q1 is connected to the anode of the diode D1, the emitter is connected to the power supply V +, and the collector is provided with the output terminal Vo. Further, the base is connected to the collector of the transistor Q2, the emitter is connected to the collector of the transistor Q1, the collector is connected to the emitter of the transistor Q2, and the output is controlled by the collector potential of the transistor Q2. A transistor Q3 is provided which branches a predetermined current from the power current and supplies it to the reference potential via the resistor R2.

In the switch circuit thus constructed, when the transistor Q2 is turned on and a current flows as described above, the collector potential of the transistor Q1, that is, the output potential Vout tends to rise.

[0023]

[Equation 6] At this point, current starts to flow through the emitter of the transistor Q3. This current is returned to the emitter of the transistor Q2 through the collector. Ignoring the base current I _B4 of the transistor Q3, the relation of each current is as follows.

[0024]

[Equation 7] Is obtained. Here, assuming that β is sufficiently larger than 1, the equation (5) becomes the following equation.

[0025]

[Equation 8]

The equation (8) is equivalent to the equation (4) shown in the conventional example. Also, when the transistor Q2 is turned off, the collector potential Vc rises, but at the same time, the collector potential of the transistor Q3 becomes V-.

As described above, the switch circuit of this embodiment is
Since the collector potential of the transistor Q3 is always the lowest potential even when the transistor Q2 is turned off, the potentials of the collector and the emitter are not reversed.
A parasitic PMOS generated by reversing the potentials of the collector and the emitter is not configured, and malfunction does not occur.

Although the PNP transistor is used in the output stage in this embodiment, the present invention is not limited to this, and the NP transistor is used.
It is needless to say that the same effect can be obtained by using the N-transistor, and various modifications and applications can be made without departing from the scope of the invention.

[0029]

As described above in detail, according to the present invention, it is possible to provide a switch circuit having a clamp function, which is suitable for integration without forming a parasitic element.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a switch circuit as an embodiment according to the present invention.

FIG. 2 is a diagram showing a configuration of a switch circuit using a conventional PNP transistor.

FIG. 3 is a diagram showing a configuration example of a switch circuit configured to solve the problem of the switch circuit shown in FIG.

FIG. 4 is a diagram showing a connection example in which a diode is composed of an NPN transistor and a PNP transistor.

[Explanation of symbols]

Q1, Q2, Q3 ... Transistors, D1, D2 ... Diodes, R1, R2 ... Resistors.

Claims (1)

[Claims] 1. A first transistor driven by an input signal, having a collector connected to a power supply via a diode and a first resistor and an emitter connected to a reference potential via a second resistor; A second base whose base is connected to the anode and which outputs a predetermined potential or is switched to an open state in response to the driving of the first transistor.
Of the first transistor, the base of the first transistor is connected to the collector, the collector of the second transistor is connected to the emitter, the emitter of the first transistor is connected to the collector, and the first transistor is turned on. Sometimes the second
And a third transistor that controls the collector-side potential of the transistor to a constant potential, and a switch circuit with a clamp function.