JPS58224416A - Pcm reproducing device - Google Patents

Abstract

PURPOSE:To obtain a PCM reproducing device having low probability to generate a different sound in a reproducing signal, by selecting a demodulating circuit in accordance with the number of times of error generation. CONSTITUTION:When an error based upon an error detecting code of a PCM reproducing signal demodulated by a demodulating circuit 4 is detected by an error detecting circuit 6, the error is corrected and compensated by an error correcting circuit 11 for an error up to two bits and an error correcting circuit 12 to compensate three bits or more. The number of error bits detected by the circuit 6 is counted up by an error counting circuit 10 and a selecting circuit 13 is controlled, so that any one of the circuits 11, 12 is selected to demodulate the selected signal by a D/A converter 7 or the like. By adopting a method using an error correcting circuit compensating easily generated different noises only when correction is impossible because of the large number of bits, the PCM reproducing device having low probability to generate a different sound in a reproducing signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PCM reproducing device, and particularly to a circuit for decoding errors among a series of circuits for extracting a recorded signal from a recording medium, demodulating it, decoding errors, and converting it into an analog signal. The present invention also relates to a PCM reproducing device with an improved circuit.

As a conventional PCM reproducing device, there is one shown in FIG. A conventional device will be briefly described with reference to FIG. The information recorded on the magnetic tape 1 is converted into an electric signal and extracted by the reproducing head 2, and the extracted electric signal is waveform-shaped by the reproducing circuit 3. The output of this reproducing circuit 3 is demodulated into a reproduced PCM signal by a demodulating circuit 4 connected to the next stage.

The output of the 91t tone circuit 4 is input to an error detection circuit 5 and an error correction circuit 6. The error detection circuit 5 detects whether or not there is an error in the demodulated reproduced PCM signal based on the error detection code included in the demodulated reproduced PCM signal, and outputs error detection information. error correction circuit 6
t, t1 This is a circuit that outputs the reproduced PCM signal sent from the demodulation circuit 4 according to a predetermined decoding method. Here, Ia@ means correcting or correcting an error portion of the reproduced PCM signal. The reproduced PCM signal that has passed through the error correction circuit 6 is sent to a digital/analog converter (
The digital signal is converted into an analog signal by the D/A converter (D/A converter) 7, amplified by the analog amplifier 8, and sent to the output terminal 9.
is output from. The above is an outline of the conventional PCM reproducing device.

Here, in order to point out the drawbacks of this conventional device and to facilitate understanding of the configuration of the present invention, which will be described later, we will explain how the demodulated PC
Error detection included in the M signal.

The code for correction and the decoding method using it must be explained in detail.

The output format of the *gti circuit 4 shown in the conventional example of FIG. 1 has a configuration shown in FIG. 2, for example. In this configuration example, the magnetic tape is divided into 8 tracks, and information is distributed and recorded on each track, consisting of a fixed number of bits (16 x 8 bits in the example in Figure 2). (referred to as a "frame"), a synchronization mark "S" for signal synchronization and a redundant bit "C" for error detection are added. And each symbol D1 of the first to sixth tracks
~D48 corresponds to information for one sample of each PCM signal, and 7th. Pl and P2 of the eighth track are redundant bits for error correction added to the information of the first to sixth tracks.

It is assumed that the redundant bits C for error detection are composed of, for example, a CRC code. This CRC code is generated by the generator polynomial G
(X) G (X) -X"+X1'L+X"
corresponds to CRC codes have the ability to detect errors with a probability of 12-+6.

It is assumed that redundant bits P1 and P2 for error correction are composed of Reed-Solomon codes, for example. An explanatory diagram of this Reed-Solomon code is shown in FIG. As shown in Figure 3, the Reed-Solomon code divides the PCM data section into 4-bit units and uses Galois fields (
24), the 7th. This is a code for calculating the recording bit of the 81st rack. That is, a, −Σ a, α.

I・1 Period a, α1+a2α2+...a6α6a6- effect al -a, +a 2+...+a.

Here, al is the value of the Galois field (24) (4-pits I configuration), and α1 is the power of the primitive light α of the primitive polynomial X′ +X+1. And this a? +aa is each PI.

5- Redundant bit C and error correction redundant bit P1 composed of Reed-Solomon code. How errors are detected and corrected by P2 will be explained.

The reproduced PCM signal output from the demodulation circuit 4 is input to the error detection circuit 5 as described above, and in this error detection circuit 5, it is detected by the redundant bit C for error detection composed of the CRC code included in the reproduced PCM signal. The presence or absence of errors in the signal is detected and output as error detection information.

In the error correction circuit 6, the reproduction P input from the *m circuit 4
Errors in the signal are detected and corrected by error correction redundant bits P1 and P2 comprised of Reed-Solomon codes included in the CM signal.

Furthermore, as shown in FIG. 1, since the error detection information from the error detection circuit 5 is input to the error correction circuit 6, the error correction circuit 6 also responds to the error detection information and performs error correction on the signal. . In other words, the error correction circuit 6
It consists of a combination of a Solomon code and a CRC code, and a decoding method based on these two codes. Here, a code that is a combination of a Reed-Solomon code and a CRC code will be referred to as an R8C code, and decoding of the R8C code will be described below.

In addition, as mentioned above, in addition to simply detecting and correcting errors using the Reed-Solomon code, by adding an error detection signal using a CRC code and decoding using an R8C code,
It is clear that error detection and correction capabilities will be further improved.

Now, the decoding of the R8C code is based on the syndrome S shown in the following equation.
This is done by calculating o,81.

514r, a.

−1 Here, rl is a reproduced symbol, and when there is no error, it is equal to al as described for the Reed-Solomon code.

Now, it is divided into cases where there is an error on one track, cases where there is an error on two tracks, and cases where there is an error on three or more tracks - C1
Let's calculate syndrome SO and 81.

(1) When there is an 11-rack error If there is an error in the first track and the error is e, then r, -a, 10e.

'j'''''j (J≠1), so the syndromes so and si are 3Q-e,
(','Σ at-0)I=l sl-e l α, ('-'4 a + α
1-0)+”L, and the error value can be found.Also, α, -81/S.

By calculating , it is also possible to find out which track is in error (error detection is possible). This result is CR
The C code code error is detected and the result matches the detection result sent from the error detection circuit 5 to the error correction circuit 6 as error detection information. Therefore, only when there is a one-track error, even if a CRC code error is missed when decoding the R8C code, the syndrome So,81 can be calculated based on the result on the Reed-Solomon code side, and the error detection and Corrections can be made.

(2) When there is a two-track error If there is an error in the first track and the first track, the syndrome so, si becomes S〇−θ10e +1 Sl−θ, α1+θ, αJ, and the error value is e I− (S1+SOαJ 〉/(α1+αj)ej
“”6t+s.

becomes. Here, α1. Since αj is determined by the detection result of the CRC code sent as error detection information from the error detection circuit 5), the error values e, . . . eJ are determined and error correction becomes possible.

If a CRC code error is missed, the Reed-Solomon code side can only detect up to one track error, so the syndrome calculates Cr -81/S O by the calculation in (1) above. However, since this does not match the CRC code error detection result, only a missed CRC code error is detected.

Based on the above results, it is 1! using R8C code! ! @ is made.

(3) If there are errors of 31-rack or more, correction is impossible with the R8C code, and correction processing is performed.

The above is a case where the decoding ability of the R8C code is utilized to the maximum, and this will be referred to as decoding method A. Decoding method A
The decoding ability of the composite ability table is shown in the decoding method section.

On the other hand, in code decoding, if the decoding ability is used to the maximum, the reliability of decoding decreases, so it is also possible to perform decoding that does not use the decoding ability to the maximum. That is, the RS Crf
In the decoding of @, if there are errors in two or more tracks, correction is impossible and correction processing is performed. This decoding will be referred to as decoding method B, and will be shown in the decoding capability table along with the vIN method 8 mentioned above.

10- Decoding ability table (K2S) In the composite ability table, rOKJ, rTJ, rMJ, “C
” represents the following meaning.

OK... Correct] -1... Correction (Corrected to correct data. Normal sound.) M... Ill correction, error detection missed (An abnormality has occurred.)
C... Correction (errors are corrected by mean value interpolation, etc.).

A correction sound occurs. ) Let's compare decoding method A and decoding method B with reference to this decoding ability table. For example, the number of error frames is 1.0R.
When the number of error detection frames on the C code side is 1, errors can be corrected by both decoding method A and tI coding method B, and
It is indicated as "T".

Next, the number of error-occurring frames is 1. Even if the number of CRC code error detection frames is 0, that is, a cRc code error is missed, the error can be detected on the Reed-Solomon code side as described above, so both decoding methods A and B correct the error. The number of error frames is 2. If the number of CRC code error detection frames is 2, according to the post-coding method, error correction is possible as described above and is ITJ, but in decoding method B, if there is an F error on more than 2 tracks, correction is possible. is impossible, and correction 51!11! I! is performed and is indicated by the correction symbol rGJ. Also, if the number of error frames is 2, CR
The number of error detection frames on the C code side is 1. When the number of missed error frames is 1, a missed CRC code error is detected in both vI month methods A and B, and correction processing is performed. The number of error frames is 3. The number of error detected frames is 2. When the number of missed error frames is 1, error correction is performed in the decoding method, and correction is performed in the decoding method B. When the number of CRC code error detection frames is 2, the decoding method uses
This is because missed GRO code code errors cannot be detected on the Solomon code side, and correction is impossible with decoding method B, so correction is performed. In general, when the number of error-generated frames is K (K2S), the results shown in the decoding ability table will be obtained depending on the number of error-detected frames.

As is clear from the above explanation, although the decoding method has very good correction ability, it has the disadvantage that the probability of erroneous correction increases when there are many errors, and this erroneous correction causes the PCM signal to change. Abnormal noises are often mixed into the reproduced sound. On the other hand, according to No. 11 B, the number of erroneous corrections is reduced even when there are many errors, but since the error correction ability is low, corrections are often made, and the problem is that correction sounds are generated more frequently. In this way, both decoding methods A and B have advantages and disadvantages depending on the error occurrence state.

By the way, as already explained, the conventional PCM playback device is equipped with only one error correction circuit no matter what error occurs, and uses one decoding method to correct vI.
Since it was @, it had the disadvantage that abnormal noises and correction sounds were often generated.

The present invention has been made in order to eliminate the drawbacks of such conventional PCM reproducing devices.

To put it simply, this invention provides a plurality of error correction circuits that configure different decoding methods when demodulated PCM signals are subjected to wI coding in an error correction circuit, and outputs of the mat circuit are sent to the plurality of error correction circuits. The present invention is a PCM reproducing apparatus which is capable of transmitting 14-m signals and is capable of selecting an error correction circuit of an optimal decoding method depending on the number of errors detected by an error detection and counting circuit.

The present invention will be described in more detail below based on embodiments with reference to the drawings.

FIG. 4 shows a PCM reproducing apparatus according to an embodiment of the present invention.

First, the overall configuration and operation of this PCM playback device will be explained. A reproducing head 2 comes into contact with the magnetic tape 1, and the information recorded on the magnetic tape 1 is converted into an electrical signal by the reproducing head 2, and the waveform is shaped by a reproducing circuit 3. The output of the reproduction circuit 3 is demodulated into a PCM signal by a demodulation circuit 4 connected next. **The output format of the circuit 4 has the same configuration as that shown in FIG. 2 of the conventional example described above, and error detection and error correction codes are also demodulated. The output of the v1w4 circuit 4 is input to the error detection circuit 5 and also to the error correction circuits 11 and 12 at the same time. As described above, the error detection circuit 5 is a circuit that detects whether or not there is an error in the reproduced PCM signal demodulated based on the error detection code. The output of this error detection circuit 5 is transmitted to error correction circuits 11 and 12 as error detection information. The error correction circuit 11 is configured with decoding method A, for example, and performs decoding with excellent correction ability. Further, the error correction circuit 12 is configured with decoding method B, for example, and performs @ code with less error correction. In this embodiment, there are two error correction circuits, the error correction circuit 11 that constitutes the decoding method and the error correction circuit 12 that constitutes the decoding method B, but the error correction circuit that constitutes the different decoding method Of course, it is possible to increase the numbers in parallel, and it is also possible to use a decoding method other than decoding methods A and B as the decoding method of the correction circuit. The outputs of the error correction circuits 11 and 12 are selected by the selection circuit 13.

The output of the error detection circuit 5 is also transmitted to the error counting circuit 10. The error counting circuit 10 is, for example, a v4 shown in FIG.
I am becoming successful. In FIG. 5, error detection information from error detection circuit 5 is transmitted to input terminal 111. This error detection information is at a high level during an error period, and is at a low level when there is no error. Depending on whether there is an error or not, the gates 102 and 10
3. With the combination of 104, the error number counting circle clock B is counted in up count mode or down count mode. More specifically, the error detection information input terminal 111
When there is an error, the output of OR gate 103 remains at a high level, and the output of OR gate 104 causes counter 106 to operate in a down-count mode. Furthermore, when there is no error in the error detection information input terminal 111, the output of the OR gate 104 remains at a high level, and the output of the OR gate 104 remains at a high level.
The counter 106 operates in the amplifier count mode by the output of 3. The mode of operation of this up/down counter 106 is shown by waveform (0) in the time chart of FIG.

For convenience of illustration and explanation, up/down counter 10
6 is assumed to perform a counting operation in the range of "0" to "4". When the content of the counter 106 is "4", the output QC of the counter 106 becomes high level, and the OR gate 105 outputs the error count clock () for the error signal (a).
b) Do not allow 17- to pass through. Therefore, the contents of the up/down counter 106 will not increase by more than "4" and will not increase by "4" or more.
4” is retained. On the other hand, the content of the counter 106 is rOJ
When , the inverted output of the output terminal BO is the inverter 10
7 and a high-level output is applied to the reset terminal R, and the counter 106 enters the reset state, thereby operating to hold rOJ even if the counter 106 counts down further.

When the content of the counter 106 becomes "0", an inverted output (e) is obtained from the output terminal BO, and this output (8) is inverted and given to the set input of the flip-flop 106, which sets the flip-flop 109. and set the selection signal (f) to high level. In addition, the counter 106
When the content of becomes r4J, a high level output is obtained from the output terminal QC of the counter 106, and the inverter 108
The output (d) is inverted and given to the reset input of the flip-flop 109, which resets the flip-flop 109 and makes the selection signal @(f) low level. .

In addition to the above configuration, the error counting circuit 10 has a counter for counting the number of errors, as shown in FIGS. 7 and 8 as a simple configuration and a time chart. The count value may be compared with a predetermined value at regular intervals, and the counter white paper may be reset immediately thereafter, and the level of the selection signal may be determined based on the comparison result.

The selection circuit 13t selects either the LiR error correction circuit 11 or the error correction circuit 12 according to the output signal of the error counting circuit 10 and sends the reproduced PCM signal to the next connected D/A converter 7. Communicate. D/A
In converter 7, the signal is converted from a digital signal to an analog signal, amplified in analog amplifier 8, and output terminal 9.
A signal is emitted from the

Although a magnetic tape is used as the recording medium in the above embodiment, it is of course possible to use other recording media such as a digital audio disk.

As described above, according to the present invention, the optimal error correction circuit is selected depending on the error occurrence state of the reproduced PCM signal, so that a PCM reproduction mode with a low probability of causing excitement in the reproduced signal is provided. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional PCIVI reproducing apparatus, and FIG. 2 is a diagram of an output A-mat of a W4 tone circuit in a PCM reproducing apparatus. FIG. 3 is a diagram of the Reed-Solomon code. FIG. 4 is a block diagram of a ROM reproducing system according to an embodiment of the present invention. FIG. 5 is a block diagram of one embodiment of the error stitch count circuit 10, and FIG. 6 is a time chart diagram of FIG. Furthermore, FIG. 7 is a diagram showing another embodiment of the error counting circuit 10, and FIG. 8 is a time chart diagram of FIG. 1 and 4, 1 is a magnetic tape, 2 is a playback head, 3 is a playback circuit, 4 is a demodulation circuit, 5 is an IM detection circuit, 6, 11, 12 is an error correction circuit, and 7 is a digital 8 is an analog amplifier, 9 is a reproduction output terminal, 10 is an error counting circuit, and 13 is a selection circuit. Note that in FIGS. 1 and 4, -I@ indicates the same or corresponding parts. Agent Shin Kuzuno - (1 other person) 21- 87 Riraku 52

Claims (1)

[Claims] A recorded signal is extracted from a recording medium in which the signal is digitally encoded and recorded with error detection and correction codes added, and 1! [lI] A pulse code modulation (hereinafter referred to as rPCMJ) reproduction unit that converts into an analog signal, which includes a circuit for extracting the signal recorded on the recording medium, and a demodulation of the signal extracted by the extraction circuit into a PCM signal. a circuit connected to the demodulation circuit to detect and count errors based on the error detection code included in the demodulated PCM signal; and a circuit connected to the demodulation circuit to detect and count errors based on the error detection code included in the demodulated PCM signal; , a circuit that decodes according to a predetermined decoding method, the decoding circuit has decoding circuits of at least two different decoding methods connected in parallel to the 111 circuit, and further, the error detection and counting circuit a circuit that selects a decoding circuit that is most suitable for the error occurrence state from among the at least two decoding circuits according to an output that indicates the counted error occurrence degree; and a circuit that converts the output of the selected decoding circuit into analog. A PCM playback device equipped with