JPS58224380A - Video memory clear circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a video memory clear circuit, and particularly to a video memory clear circuit that uses video memory scanning to quickly clear the entire contents of the video memory. be.

(2) Background and problems For example, CRT graphic screens such as CRT displays tend to have higher density year by year in order to display clear images.
There are also devices that have a 40x400 dot configuration and allow you to specify the three primary colors of red, green, and blue. As graphics become more dense, a problem arises. That's CP
The problem is that as the amount of information increases, the CPU processing time will take longer. That is, as the number of dots on the CRT increases, the time required to read and write data to the video memory also increases.

In particular, processing to clear the display screen is frequently required, but in the past, the CPU sequentially specified the addresses of the video memory and wrote "0" into all areas. Therefore, access to the entire video memory is
As the number of dots increases and the density increases, more processing time is required.

(3) Purpose of the Invention The present invention aims to solve the above-mentioned problems, and specifically aims to speed up the processing of the clear function, which is one of the basic functions in CRT processing.

(4) Structure of the Invention In order to achieve the above-mentioned object, the present invention utilizes video memory scanning to speed up the processing of the clear function, which was conventionally realized by software, by converting it into hardware. That is, the video memory clear circuit of the present invention has at least an address signal terminal into which an address supplied from the video scan/address creation circuit or the central processing unit is input, a read/write signal terminal, and a data input/output terminal. The circuit has a video memory in which image data of the display is stored, and the circuit includes a latch circuit that is latched by a signal from the central processing unit, and the output of the latch circuit supplies a write signal to the read/write signal terminal. At the same time, it is configured to fix the input level of the data input/output terminal,
The present invention is characterized in that the video memory is cleared by scanning the video memory for at least one screen using at least the address signal supplied by the video Φ scan address generation circuit. Hereinafter, embodiments will be described with reference to the drawings.

(5) Embodiment of the Invention FIG. 1 shows a schematic configuration of an embodiment of the invention, and FIG. 2 shows a detailed circuit of an embodiment of the invention. In the figure, 1 is a CPU, 2 is a video memory composed of, for example, a refresh memory, and 3 is a CPU.
is a read/write signal terminal, 4 is a data input/output terminal, and 5 is a data input/output terminal.
is a video scan address creation circuit that creates an address for scanning video memory 2, 6 is a multiplexer that selects an address for video memory 2, 7 is a clip flop, and 8 is a normal data input/output processing and clearing circuit. Switching unit for switching processing, 9-1.9-2゜10-
1.10-2 represents a tri-state buffer, and 11 represents a multiplexer for switching the output destination of data.

In FIG. 1, when the contents of the video memory 2 are displayed on a CRT display (not shown), the address of the video memory 2 created by the video scan address creation circuit 5 is transferred to the video memory 2 via the multiplexer 6. The image information is supplied to the memory 2, and the image information is sequentially read out by scanning and displayed. When changing the image, the CPUI supplies the address of the video memory 2 to be changed to the multiplexer 6, and the multiplexer 6 selects this address signal and supplies it to the video memory 2. It outputs a write signal to the read/write signal terminal 3 of the video memory 2.

For example, read/write signal terminal 3KH level (rlJ
) means a read signal, and when an L level (rOJ) signal is supplied, it means a write signal. By supplying the write signal, the data supplied to the data input/output terminal 4 is written to the address of the video memory 2 specified by the address signal 2. The CPU reads the contents of the video memory 2. In this case, the address signal is similarly supplied via the multiplexer 6, and the read/write signal terminal 3 is
By supplying the level signal, data at the designated address is read out to the data input/output terminal 4.

Conventionally, when clearing all the contents of the video memory 2, software sequentially specified all addresses to the CPU, and in the same way as normal data writing,
0" data was written to all areas. However, in the present invention, the CPU simply sets the flip 70 knob 7, and the entire area is automatically cleared to "0" by the switching unit 8, as will be described later.

In FIG. 2, normal data input/output will be explained first. For normal data input/output, flip
The flop 7 is in a state where it outputs Q21 and S=0 by the reset signal supplied to the preset terminal PR. The Q=1 output of clip flop 7 is
It is used as a strobe input for tri-state buffers 10-1 and 10-2. Therefore, at this time, tri-O state buffers 10-1 and 10-2 are in a state of no impedance. Further, the output of Q=0 is supplied to tri-state buffers 9-1 and 9-2, and the CPU is connected to the read/write signal terminal 3 and data input terminal 4-2 of the video RAM 2. state. That is, the circuit connection configuration is similar to the conventional one, and the read or write signal supplied from the CPU is input to the read/write signal terminal of the video memory 2, and the read or write signal is input to the data output terminal 4-, respectively. Data is read from the terminal 1 or data is written from the data input terminal 4-2.

When setting all the contents of the video memory 2 to O and clearing the image displayed on the display, the CPU 1 supplies the flip-flop 7 with a latch select signal selected in association with a specific address. At the rising edge of this latch select signal, the grounded terminal goes low.
Since it indicates the level, the flip-flop 7 will output Q=O and Q=1. With the output of mutual=1, tri-state buffers 9-1 and 9-2
The impedance becomes high, and the CPUI is disconnected from the read/write signal terminal 3 and the data input terminal 4-2. Also, by supplying the output of Q=0 to the tri-state buffers 10-1 and 10-2, the read/write signal terminal 3 of the video memory 2
and data input terminal 4-2 are at 0 level (L level) without being grounded. When the read/write signal terminal 3 becomes L level, the video memory 2 performs a process of writing the value of "0" inputted from the data input terminal 4-2 to the designated address. On the other hand, when there is no access from the CPU 1, the address supplied to the video memory 2 is generated by the video scan address generation circuit 5 shown in FIG. 1, and is selected by the multiplexer 6. This address is updated sequentially to indicate the entire area of the video memory 2 according to the scan cycle, so at least the video memory 2
While the entire area of the video memory 2 is being scanned, if the flip-flop 7 is outputting Q=0 and Q=1, "0" is automatically written to the entire area of the video memory 2, and the display screen is cleared. The Rukoto. After scanning one screen or more, the clip flop 7 is reset by a reset signal to output Q=1 and Q=0, and the normal video memory 2 can be accessed again. return.

It goes without saying that the present invention is not necessarily limited to video memories used for graphic displays, but can also be applied to video memories used for character displays.

(6) Detailed Description of the Invention According to the present invention, it is possible to clear the entire contents of the video memory at extremely high speed using hardware. Also, the instructions for clearing the
For example, since it can be processed using the l instruction, it is also easier to create a program.

[Brief explanation of the drawing]

FIG. 1 shows a schematic configuration of an embodiment of the invention, and FIG. 2 shows a detailed circuit of an embodiment of the invention. In the figure, 1 is a CPU, 2 is a video memory, 3 is a read/write signal terminal, 4 is a data input/output terminal, 5 is a video scan address generation circuit, 6 is a multiplexer, 7 is a clip flop, and 8 is a Switching section, 9-1.9-2.1
0-1.10-2 is the tri-state buffer, 11
represents a multiplexer. Patent applicant Fujitsu Limited

Claims (1)

[Claims] The image data of the display is stored, which is equipped with at least an address signal terminal into which an address supplied from the scan address generation circuit or central processing unit of this video is input, a read/write signal terminal, and a data input/output terminal. A circuit having a video memory comprising a latch circuit latched by a signal from the central processing unit, the output of the latch circuit supplies a write signal to the read/write signal terminal, and the output of the data input/output terminal. The video is configured to fix an input level, and the video memory is cleared by scanning the video memory for one screen or more using at least an address signal supplied by the video scan address generation circuit. Memory clear circuit.