JPS58223968A - Black frame inserting circuit - Google Patents

Black frame inserting circuit

Info

Publication number
JPS58223968A
JPS58223968A JP10810782A JP10810782A JPS58223968A JP S58223968 A JPS58223968 A JP S58223968A JP 10810782 A JP10810782 A JP 10810782A JP 10810782 A JP10810782 A JP 10810782A JP S58223968 A JPS58223968 A JP S58223968A
Authority
JP
Japan
Prior art keywords
black frame
transistor
signal
input
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10810782A
Other languages
Japanese (ja)
Inventor
Akiyoshi Maeda
朗善 前田
Tetsuo Motomura
元村 哲夫
Fusao Ushio
潮 房雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10810782A priority Critical patent/JPS58223968A/en
Publication of JPS58223968A publication Critical patent/JPS58223968A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/272Means for inserting a foreground image in a background image, i.e. inlay, outlay

Abstract

PURPOSE:To quicken the response time, by connecting each one end of the 1st and the 2nd resistors connected to each emitter of transistors (TRs) to each base of which a vidio signal and a black frame signal are inputted respectively and connecting an output terminal to the connecting point of the resistors. CONSTITUTION:A video signal of negative polarity is applied to a terminal 20, and a black frame inserting signal is applied from a terminal 29. A reference potential Vref is equal to a pedestal level of input signal of negative polarity. Trs 21, 25, resistors 23, 24 and a constant current source 22 constitute an attenuator circuit and Trs 27, 28, 30, 31 resistors 32, 33, 34 and a constant current source 26 constitute a switching circuit. The black frame inserting signal is set to a low level when being inserted and to high level when being not inserted.

Description

【発明の詳細な説明】 不発明は、映出された画像の任意の位置に黒枠部を挿入
るよう映像信号に黒枠を挿入する黒枠挿入回路に関する
もので挿入された黒枠自体の部分の映像も見えるように
構成したものである。
[Detailed Description of the Invention] The invention relates to a black frame insertion circuit that inserts a black frame into a video signal so as to insert a black frame at an arbitrary position in a projected image, and also includes an image of the inserted black frame itself. It is designed so that it can be seen.

従来の黒枠挿入回路例を第1図に示す。この回路は、i
E正極性映像信号が入力端子1より加えられる。黒枠挿
入を行なわないときには、入力映像信はトランジスタ2
と抵抗3より構成されるエミノタフズロア回路および抵
抗4を通り出力端子11より出力される。このとき、抵
抗6とトランジスタ6で構成されるスイッチ回路はOF
Fの状態であり、トランジスタ6は遮断領域にある。一
方、黒枠挿入を行なうとき、黒枠挿入信号が挿入信号端
子10に加わり高電位になる。このときトランジスタ6
は飽和領域動作となり、出力端子11での電位は、はぼ
定電圧源7で定まる値となり、この値を出力信号のペデ
スタルレベルに一致させることにより黒枠の挿入を行な
っていた。従って従来回路では、黒枠のレベルが常にペ
デスタルレベルになること、および、黒枠挿入時にスイ
ッチング動作を行なうトランジスタ5が遮断領域から飽
和領域への動作に移行する為、応答時間の遅いことが問
題点であった。
An example of a conventional black frame insertion circuit is shown in FIG. This circuit is i
E A positive polarity video signal is applied from input terminal 1. When not inserting a black frame, the input video signal is connected to transistor 2.
The signal is output from the output terminal 11 through the Emino Tough's lower circuit consisting of the resistor 3 and the resistor 4. At this time, the switch circuit composed of the resistor 6 and the transistor 6 is OF
F state, and transistor 6 is in the cutoff region. On the other hand, when inserting a black frame, a black frame insertion signal is applied to the insertion signal terminal 10 and becomes a high potential. At this time, transistor 6
operates in the saturation region, and the potential at the output terminal 11 is approximately determined by the constant voltage source 7, and the black frame is inserted by matching this value to the pedestal level of the output signal. Therefore, in the conventional circuit, the problem is that the level of the black frame is always at the pedestal level, and that the response time is slow because the transistor 5, which performs switching operation, shifts from the cutoff region to the saturation region when the black frame is inserted. there were.

この発明は、この問題点を改善したものでその1実施例
を第2図に示しその具体的動作を以下に説明する。負極
性の映像信号が映像信号入力端子20に加えられ、黒枠
挿入信号は挿入信号入力端子29より加えられる。また
、基準電位端イ36の基準電位の値Vrefは、負極性
の入力信号のベテスタルレベルニ等しい値になっている
。トランジスタ21と25+抵抗23と24.定電流源
22とでアッテネータ回路を構成し、トランジスタ27
.2B、30,31.抵抗32,33.34゜定電流源
26とによりスイッチング回路を構成している。黒枠挿
入信号は挿入時Lowレベルに、挿入しない時Hi g
h レベルになるように設定されている。黒枠挿入信号
が入力されていないとき、トランジスタ27のベース電
位はトランジスタ28のベース電位よりも高い値になつ
ているので、トランジスタ28がON状態となりトラン
ジスタ28のコレクタ端子より定電流源26の電流値工
1が流れ出し、トランジスタ30と31より構成される
カレントミラー回路の働きによりトランジスタ31のコ
レクタ端子に電流値工1の電流が流れ込む。そのとき、
トランジスタ26のベース端子電圧は抵抗32の抵抗値
をRs2とすると、 Vref−I+−R32となる。
The present invention improves this problem, and one embodiment thereof is shown in FIG. 2, and its concrete operation will be explained below. A video signal of negative polarity is applied to the video signal input terminal 20, and a black frame insertion signal is applied from the insertion signal input terminal 29. Further, the value Vref of the reference potential at the reference potential terminal A36 is equal to the best signal level of the input signal of negative polarity. Transistors 21 and 25 + resistors 23 and 24. The constant current source 22 constitutes an attenuator circuit, and the transistor 27
.. 2B, 30, 31. The resistor 32, 33.34° constant current source 26 constitute a switching circuit. The black frame insertion signal is low level when inserted, and high when not inserted.
h level. When the black frame insertion signal is not input, the base potential of the transistor 27 is higher than the base potential of the transistor 28, so the transistor 28 is turned on and the current value of the constant current source 26 is changed from the collector terminal of the transistor 28. Current value 1 flows into the collector terminal of transistor 31 due to the action of the current mirror circuit composed of transistors 30 and 31. then,
The base terminal voltage of the transistor 26 is Vref-I+-R32, where the resistance value of the resistor 32 is Rs2.

この値を、映像信号入力端子2oの電位よりも常に低い
値に選べば、トランジスタ26は常に遮断領域動作とな
り、エミッタフォロア動作をしているトランジスタ21
から見て抵抗24.トランジスタ261は負荷ではなく
なり、入力映像信号は抵抗23を通りトランジスタ36
.定電流源37で構成されるエミッタフォロア動作によ
り低出力インピーダンスに変換され、入力映像信号と同
じ振幅のママ映像信号出力端子38より出力される。
If this value is always selected to be lower than the potential of the video signal input terminal 2o, the transistor 26 always operates in the cutoff region, and the transistor 26 operates as an emitter follower.
Resistance 24. Transistor 261 is no longer a load, and the input video signal passes through resistor 23 to transistor 36.
.. It is converted into a low output impedance by an emitter follower operation constituted by a constant current source 37, and is outputted from a mother video signal output terminal 38 having the same amplitude as the input video signal.

黒枠挿入信号が入力されたときは、トランジスタ27の
ベース端子電位はトランジスタ28のベース端子電位よ
りも低い値であるのでトランジスタ28がOFF状態(
遮断領域動作)となり、トランジスタ30のコレクタ端
子には全く電流が流れ込まず、カレントミラー回路を構
成するトランジスタ31のコレクタ端子にも電流が流れ
込まない。したがって、トランジスタ260ベース端子
電位はVrefになる。黒枠挿入信号が入力された状態
のアッテネータ回路の働きを示し、詳しく説明するのが
第3図である0ここで映像入力信号端子20の端子電位
をvl・抵抗23と24の抵抗値をそれぞfll(Iと
R2、定電流源22の電流値をIo、トランジスタ26
のベース端子電位をVref、トランジスタ21と26
のエミッタ端子より流れ出す電流値をそれぞれl111
. IR2ベース・エミッタ間の電位差をそれぞれVg
x+ 、 VBI+2とすれは1次式が成り立つ。
When the black frame insertion signal is input, the base terminal potential of the transistor 27 is lower than the base terminal potential of the transistor 28, so the transistor 28 is in the OFF state (
(cut-off region operation), and no current flows into the collector terminal of the transistor 30 at all, and no current flows into the collector terminal of the transistor 31 forming the current mirror circuit. Therefore, the base terminal potential of transistor 260 becomes Vref. Figure 3 shows the function of the attenuator circuit when the black frame insertion signal is input, and will be explained in detail. fll (I and R2, the current value of the constant current source 22 is Io, the transistor 26
The base terminal potential of transistors 21 and 26 is Vref,
The current value flowing out from the emitter terminal of each is l111
.. The potential difference between IR2 base and emitter is Vg.
A linear equation holds for x+ and VBI+2.

Io = IE+ + II+2         −
−(1)V+ −VBIII = Vref −VBI
+2−(R+ + R2)II+2 ・・−(2)これ
を解と次のようになる0ただし、VTはビルトイン電位
であるO O ・・・・・・(3) O ・・・・・・(4) トランジスタ26のエミッタ端子より流れ出す電流11
12を(4)式を用いて直線近似すると第4図のように
なり、線形領域において、 Vat+=V+sx2とす
れとなる。これはペデスタルレベルVre f  と負
極性入力信号レベルv1との差、すなわち、入力信号の
出力する。黒枠挿入時、入力されるペデスタルレベルか
らホワイトビークまでの信号の大きさが第4図の特性の
線形領域内にくるように、抵抗23と24の抵抗値の和
と定電流値工0との積を信号のペデスタルレベルからホ
ワイトピークまでの振幅の太きさよりも大きく選はなけ
ればならない。第5図に、ランプ波aを映像入力端子2
0より入力し、黒枠挿入信号すを挿入信号入力端子29
より入力したとき、映像出力端子38より表われる信号
Cを示している。黒枠挿入時には、出力端子に倍の大き
さの信号である。第6図に、正極性の映像信号の場合の
応用例の回路を示している。この−場合、トランジスタ
46と47をPNPトランジスタにすることにより、黒
枠挿入回路を容易に構成できる。
Io = IE+ + II+2 −
-(1)V+ -VBIII = Vref -VBI
+2-(R+ + R2)II+2...-(2) The solution is as follows: 0 However, VT is the built-in potential O O...(3) O... (4) Current 11 flowing out from the emitter terminal of transistor 26
12 is linearly approximated using equation (4), as shown in FIG. 4, and in the linear region, Vat+=V+sx2. This is the difference between the pedestal level Vref and the negative input signal level v1, that is, the output of the input signal. When inserting a black frame, the sum of the resistance values of resistors 23 and 24 and the constant current value of The product must be selected to be larger than the amplitude of the signal from the pedestal level to the white peak. In Figure 5, ramp wave a is input to video input terminal 2.
Input the black frame insertion signal from 0 to the insertion signal input terminal 29.
This shows the signal C that appears from the video output terminal 38 when the signal is input from the video output terminal 38. When a black frame is inserted, a signal of twice the size is sent to the output terminal. FIG. 6 shows an application example circuit for a positive polarity video signal. In this case, by using PNP transistors as the transistors 46 and 47, the black frame insertion circuit can be easily constructed.

以上述べたように本発明により、黒枠信号挿入時に応答
時間が早く、黒枠が黒レベルまで落ちないで抵抗23と
24の抵抗値で定まる一定比率だけ信号波形が縮められ
、その背影にある映像信号も見える黒枠が得られる等の
効果がある0
As described above, according to the present invention, when a black frame signal is inserted, the response time is fast, the signal waveform is shortened by a certain ratio determined by the resistance values of the resistors 23 and 24 without the black frame falling to the black level, and the video signal behind the black frame is reduced. It has the effect of obtaining a black frame that is also visible.0

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の黒枠挿入回路の1例を示す回路図、第2
図は本発明の黒枠挿入回路の1実施例を示す回路図、第
3図は同要部の回路図、第4図と第5図は本発明の1実
施例の動作を説明するための説明図、第6図は本発明の
他の実施例の要部を示す回路図である。 20・・・・・映像信号入力端子、22,26.37・
・・・定電流源、23,24,32,33.34・・・
・・抵抗、29・・・・・・黒枠挿入信号入力端子、3
6・・・・・・基準電位端、38・・・・・・映像信号
出方端子。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 1/// 第2図 五 ref 6Wυ− 第3図 77 &AID 第4図
Figure 1 is a circuit diagram showing an example of a conventional black frame insertion circuit;
The figure is a circuit diagram showing one embodiment of the black frame insertion circuit of the present invention, FIG. 3 is a circuit diagram of the same essential part, and FIGS. 4 and 5 are explanations for explaining the operation of one embodiment of the present invention. 6 are circuit diagrams showing essential parts of another embodiment of the present invention. 20...Video signal input terminal, 22, 26.37.
... Constant current source, 23, 24, 32, 33.34...
...Resistance, 29...Black frame insertion signal input terminal, 3
6...Reference potential terminal, 38...Video signal output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1/// Figure 2 5ref 6Wυ- Figure 3 77 &AID Figure 4

Claims (4)

【特許請求の範囲】[Claims] (1)映像信号が七のベースに入力され、そのエミッタ
が定電流源と第1の抵抗に接続された第1のトランジス
タと、黒枠信号がそのベースに入力され、そのエミッタ
が第2の抵抗の一端に接続された第2のトランジスタと
、第1及び第2の抵抗の各々の他の一端が接続され、そ
の接続点に接続された出力端子とよりなることを特徴と
する黒枠挿入回路。
(1) The video signal is input to the base of the seventh transistor, and its emitter is connected to the constant current source and the first resistor, and the black frame signal is input to its base, and its emitter is connected to the second resistor. A black frame insertion circuit comprising: a second transistor connected to one end of the transistor; and an output terminal connected to the other end of each of the first and second resistors and connected to the connection point thereof.
(2)黒枠信号が入力されたとき、第2のトランジスタ
のベースの電圧が、第1のトランジスタに入力される映
像信号のペデスタル電位とほぼ等しくなることを特徴と
する特許請求の範囲第1項記載の黒枠挿入回路。
(2) When the black frame signal is input, the voltage at the base of the second transistor becomes approximately equal to the pedestal potential of the video signal input to the first transistor. Black frame insertion circuit described.
(3)黒枠信号が入力されないとき、第2のトランジス
タのベース電位が、第1のトランジスタのベースに入力
される映像信号が負極性のときは、その映像信号の最低
の電位よりも低い電位となるように設定され、第1のト
ランジスタのベースに入力される映像信号が正極性のと
きは、その映像信号の最大の電位よりも高い電位となる
ように設定されたことを特徴とする特許請求の範囲第1
項記載の黒枠挿入回路。
(3) When the black frame signal is not input, the base potential of the second transistor is lower than the lowest potential of the video signal when the video signal input to the base of the first transistor has negative polarity. and when the video signal input to the base of the first transistor is of positive polarity, the potential is set to be higher than the maximum potential of the video signal. range 1
Black frame insertion circuit described in section.
(4)第1及び第2の抵抗の抵抗値の和と、定電流源の
電流値の積が、第1のトランジスタのベースに入力され
る映像信号の最大振幅よりも大きいことを特徴とする特
許請求の範囲第1項記載の黒枠挿入回路0
(4) The product of the sum of the resistance values of the first and second resistors and the current value of the constant current source is larger than the maximum amplitude of the video signal input to the base of the first transistor. Black frame insertion circuit 0 according to claim 1
JP10810782A 1982-06-22 1982-06-22 Black frame inserting circuit Pending JPS58223968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10810782A JPS58223968A (en) 1982-06-22 1982-06-22 Black frame inserting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10810782A JPS58223968A (en) 1982-06-22 1982-06-22 Black frame inserting circuit

Publications (1)

Publication Number Publication Date
JPS58223968A true JPS58223968A (en) 1983-12-26

Family

ID=14476059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10810782A Pending JPS58223968A (en) 1982-06-22 1982-06-22 Black frame inserting circuit

Country Status (1)

Country Link
JP (1) JPS58223968A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494950A (en) * 1972-04-26 1974-01-17
JPS52126138A (en) * 1976-04-15 1977-10-22 Toshiba Corp Level shift circuit
JPS5620390A (en) * 1979-07-26 1981-02-25 Sharp Corp Controlling circuit of television superimposition screen
JPS56106477A (en) * 1980-01-30 1981-08-24 Pioneer Video Corp Circuit for inserting character in television screen

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494950A (en) * 1972-04-26 1974-01-17
JPS52126138A (en) * 1976-04-15 1977-10-22 Toshiba Corp Level shift circuit
JPS5620390A (en) * 1979-07-26 1981-02-25 Sharp Corp Controlling circuit of television superimposition screen
JPS56106477A (en) * 1980-01-30 1981-08-24 Pioneer Video Corp Circuit for inserting character in television screen

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