JPS5822342Y2 - Preset receiver writing circuit - Google Patents

Description

[Detailed description of the invention] This invention relates to a writing circuit for a preset receiving device, and is particularly devised so that writing to the memory is possible only when the preset channel selection switch is operated after the memory writing switch is operated. It is.

Hereinafter, a detailed description will be given with reference to embodiments shown in the drawings.

Reference numeral 1 denotes a main body of the radio receiving device, which includes a front end having a variable capacitance diode, an intermediate frequency amplification circuit, a detection circuit, a low frequency amplification circuit, a speaker, and the like.

For this front end, the tuning voltage (hereinafter T
An output from a Tu voltage generation circuit 3 or a readout output from a preset memory 4 in which a Tu voltage value is preset is selectively applied via a switching gate 2 (referred to as a constant voltage).

The Tu voltage generation circuit 3 starts the Tu constant voltage sweep when a sweep start signal S1 generated in response to the operation of the sweep start switch 5 is applied to the sweep drive circuit 6, and when a broadcast is received, the Tu voltage generation circuit 3 starts the Tu constant voltage sweep. When the sweep stop signal S2 generated from 1 is applied to the sweep drive circuit 6, the Tu constant voltage sweep is stopped, and thereafter the Tu constant voltage at that point in time is continuously output.

Tu voltage values corresponding to each broadcasting station can be written (preset) in the preset memory 4 in advance.

To preset, first operate the sweep start switch 5 to perform a Tu constant voltage sweep and receive the station to be preset.

Next, operate the memory write switch 7, and then operate any one of the plurality of (three in the illustrated embodiment) preset channel selection switches 8 to specify an address for the preset memory 4. Do it.

The output of AND gate 9, which was at high level when the memory write switch 7 was operated, is reversed to low level by operating the preset channel selection switch 8 and setting the output of 10 to low level. .

The fall of the output of the AND gate 9 triggers the write period setting circuit 11 configured with a monostable multi-by-break circuit, and the output thereof is inverted to a high level for a certain period of time.

The transfer gate 12 is opened by the high level output (inverted output) of this circuit 11, and at that point the Tu lightning voltage preset memory 4 is outputted from the Tuu voltage generation circuit 3.
is written to the desired address specified by the preset channel selection switch 8.

If you operate the preset channel selection switch 8 first and then operate the memory write switch 7, the Noah Gate 1
Since the output of 0 is low level, AND gate 9
The output will never go high, and writing to preset memory will not be possible.

During the write period, the high level output of the write period setting circuit 11 is applied to the OR gate 13, so the output from the Tu electric voltage generation path is applied to the front end, and when the write period ends, the output of the circuit 11 is applied to the OR gate 13. When becomes a low level, the output of the inverter circuit 14 becomes a high level and the AND gate 15 is driven, and the output of the AND gate 15 switches the Tuu pressure switching gate 2. The readout output of the preset memory 4 is applied to the front end via this gate 2.

After presetting the Tu lightning voltage in the preset memory 4 in this way, simply operating the preset channel selection switch 8 will turn on the OR gate 16 and the AND gate 15.
is driven, thereby the Tuu pressure switching gate 2 is switched, and the readout output of the preset memory 4 is applied to the front end via the gate 2, allowing preset reception of a desired station.

If you further operate the sweep start switch 5, OR gate 1
3 is driven and the gate 2 is switched, so that the swept Tu lightning voltage output from the Tuu pressure generating circuit 3 is applied to the front end through the gate 2 and can be received by normal sweep. .

Incidentally, the flip-flop circuit 17 connected after the switches 5, 7.8 is for holding the operation output of the switch, and when one switch is operated, the flip-flop circuit connected to the other switch is 17 is configured to be cleared.

Further, as the preset memory, a MOS-FET can be used as a non-repellent analog memory.

The features of the present invention described above are that writing to the preset memory is possible only when the memory write switch is operated first, and then the preset channel selection switch is operated;
The point is that writing is disabled when the order of switch operations is reversed.

If the configuration is such that writing is possible even when the memory write switch is operated after the preset channel selection switch is operated, the following inconvenience will occur.

Now, suppose that after operating the sweep start switch 5 to drive the Tuu pressure generation circuit 3 and receiving the broadcast to be preset, first operate the preset channel selection switch 8 to specify an address for the preset memory. At this point, the contents preset at this address are read out and applied to the front end via gate 2.

Thereafter, when the memory write switch 7 is operated, the output of the Tuu pressure generation circuit 3 is applied to the front end via the gate 2 and is also written into the preset memory 4.

That is, from the time the preset channel selection switch 8 is operated until the memory write switch 7 is operated, the reception state is different from the broadcast to be actually preset, which is extremely inconvenient.

According to the present invention, such inconveniences can be prevented.

[Brief explanation of drawings]

The figure is a block diagram of a write circuit of a preset receiving device according to the present invention. 1 is a radio receiving device main body having a front end etc., 2
3 is a tuning voltage switching gate, 3 is a tuning voltage generation circuit, 4 is a preset memory, 5 is a sweep start switch, 7 is a memory write switch, 8 is a preset channel selection switch, 10 is a NOR gate, and 11 is a write period setting circuit.

Claims (1)

[Scope of utility model registration request] A tuning voltage generation circuit that generates a tuning voltage applied to a front end having a variable capacitance diode, a memory that stores a tuning voltage value generated by this tuning voltage generation circuit or a value equivalent to this, and a memory for this memory. a preset tuning switch for specifying an address; a memory writing switch for instructing writing to the memory; and a memory writing switch that is driven in response to the operation of the memory writing switch and the subsequent preset tuning switch to keep the memory constant. a write period setting circuit that sets a write-enabled state for only a period;
A write circuit for a preset receiving device, comprising a circuit that blocks driving of the write period setting circuit when the memory write switch is operated after operating the preset channel selection switch.