JPS58222783A - Energization command generator for power converter - Google Patents

Abstract

PURPOSE:To enable to readily alter the frequency, amplitude, phase and waveform of an energization command signal by obtaining the command signal of variable phase which is subjected to pulse width modulation. CONSTITUTION:An energization command generator 6 has a latch circuit 61 which receives upper bit group data of theta0 of an inputted reference signal and produces an upper phase signal thetaH, and a pulse width modulator 62 which inputs a lower bit group data of the signal theta0 and produces a lower phase signal thetaalpha pulse-width modulated. These outputs and hence the upper and lower phase signals thetaH, thetaalpha are added by an adder 63, and a repetitive phase angle signal theta1 is inputted together with an energization control signal S to a memory circuit 64. The signal S from the memory circuit 64 and a digital energization command signal D outputted corresponding to the time change of addressing to the phase signal theta1 are analog converter by a D/A converter 65, and harmonic components are removed by a filter 66, thereby obtaining an energization command signal NS.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply command generator for a power conversion device such as a cycloconverter or an inverter, and in particular, it is capable of controlling the frequency, amplitude, and phase of an output voltage or output current. This is an attempt to improve the power supply command generator that can be used.

Figure 1 shows an example of the configuration of a general three-phase power supply type transistor inverter.
(2) is the load, (8) is the power conversion main circuit consisting of
) is a transistor drive circuit, (4) is an energization control circuit, (
5) is a power supply command generator, which generates a frequency signal F and a voltage or current amplitude setting signal Vs(
Each phase power supply command signal vf1u (1, u
) ~ "5W (ISW), and this power supply command signal vB u ('811) ~ ■BW (IBM
), the energization control circuit (4) obtains energization control signals SU to S6, and further, the energization control signals S□ to S are shaped and amplified by the transistor drive circuit (8), and the transistors T□
By performing on/off control of T6), a desired power supply voltage or power supply current can be obtained.

Normally, when controlling the power supply current to a desired level, a current detector for each phase is installed and current feedback closed loop control is performed. The instantaneous value of the actual output voltage has a waveform with many harmonic components, but when viewed in terms of the instantaneous average voltage, it is possible to perform follow-up control to the power supply command signal. Also,
It is known that when performing this power supply current control, if the load is inductive, control can be performed with less harmonic content and less deviation between the power supply command signal and the output current.

Fig. 2 shows the configuration of a conventional example of the power supply command generator (6), in which φI) is a pulse counter, a ring, - is a memory circuit, and 2) is a digital-to-analog converter (hereinafter D).
/ A converter), Q) 6), 17) are multipliers, 1
Reference numeral 1581 denotes an adder, and in the power supply command generator (6) equipped with these components, first, the pulse counter 4) inputs and integrates the frequency signal F consisting of a variable frequency pulse train, and calculates the integrated result at a predetermined division ratio. A phase signal θ having the divided output frequency is obtained and sent as an address input to the memory circuit. The mesori circuit H (54i) stores data expressed by the following formula for the phase signal θ.

σ = blood θ ... (1) θ = K
sin (θ1−π) @z(g)6 □The phase signal θ8 and the phase signal 0v are output as data output signals, and these data output signals θ□.

0 is converted into an analog phase signal θuAI'VA by the D/mu converter (2) and (2) and then converted to an analog phase signal θuAI'VA (which is then sent to the multiplier).

ml each.

Therefore, the multiplier ■, 17) inputs the analog phase signals ζA, ev□ as well as the amplitude setting signal Vs (or Ig) input to the power supply command generator (6), and by multiplying these, the U phase After obtaining the power supply command numbers v, u (1, u) and the V-phase power supply command signal vli V (' 8 V), i
+(Fl 4・4.

vsw(1av) is calculated by p using the following formula.

■8'W(IBW)=-(vllu('au)” ■
8V (111V) )...(8) However, the conventional power supply command generator (5) has the above configuration.
Therefore, the frequency is the frequency signal F, and the amplitude setting signal Vs (
It is possible to obtain a power supply command signal having a desired waveform such as a sine wave, a staircase wave, a trapezoidal wave, etc. by setting the power supply command signal manually or manually.
Although it is possible to obtain a phase signal θ and a signal with a fixed phase,
It was not possible to obtain a variable phase signal for the phase signal θ, and therefore it was not possible to control the phase according to the load conditions.

Therefore, the present invention was made to solve the problems of the conventional ones as described above, and it is possible to obtain a power feeding command signal with a variable phase for the phase signal σ, and also to
This paper proposes a power supply command generator that can easily change the amplitude, phase, and waveform.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing the configuration of an embodiment of the power supply command generator (6) according to the present invention. In the figure, the desk indicates θ of the input reference phase signal. The upper bit group data is taken) and the upper phase signal θ is obtained.
The latch circuit that obtains the above reference phase signal θ. The lower phase signal σ is input with the lower bit group data of , and the pulse width is changed by y4. M is the upper phase signal aH and the lower phase signal θ.
A phase signal that is a repeated phase angle signal by adding α, −
The adder that obtains 0, - is the power supply control signal S that selects the amplitude, phase, and waveform, and the phase signal σ□ output from the adder -.
This is a memory circuit which stores the data of the power feed command signal corresponding to the address input and the address input, and from this memory circuit The output digital power supply command signal is converted into an analog signal by a D/A converter, and harmonic components are removed by a filter before being output.

In the above configuration, the memory circuit stores data of a staircase wave as shown in FIG. 4, which shows the relationship between the phase signal θ It stores data that allows the phase, amplitude, and waveform to be arbitrarily set for the phase signal θ□. Then, the phase signal θ□ can be repeatedly increased or decreased in time to give an instantaneous phase, and by making the repeated difference variable, it is possible to obtain an arbitrary power supply command signal with a variable frequency. being done. Here, the phase, amplitude, and waveform are selected by selecting a series of data stored in advance using the power supply control signal S, which is a signal of the upper bit group of the memory circuit ((4). For example, as shown in FIG. If the amplitude and waveform are the same as the function H) shown in the figure, but only the phase is changed, it is sufficient to store the data of the function ←2 shown in the same figure, and the power supply control signal S can be used to It is possible to choose the ship's side.

Next, the generation of the phase signal θ□ will be explained. FIG. 4 shows the reference phase signal σ. is a signal indicating an instantaneous phase angle with a variable period given by a setting device (not shown); Po is a carrier pulse; Pck is a clock pulse;
The data of the upper bit group of the command phase signal C6 is taken in at the latch circuit FMr (611), and the data is sent to the latch circuit (611).
〃 allows the upper phase signal θyo to be obtained, and the reference phase signal σ.

The data of the lower bit group is input to a PWM modulator, and the lower phase signal IPa is obtained by this modulator. Here, the carrier pulse P is a pulse train having a constant line repetition period, and obtains the data acquisition timing of the latch circuit (6) and the data acquisition timing of the PWM modulator (2).

The PWM modulator unit for obtaining the lower phase signal 1IPa is composed of a counter and a signal processing circuit (not shown), and outputs the reference phase signal σ for each carrier pulse P0. The built-in counter normally counts pulses from the preset time, and the counter integrated value decreases until it finally reaches zero. Here, the clock pulse P. k
is the period of the carrier pulse period divided by the number of states of the lower bit group data. For example, if the lower bit group data is n-bit data, the number of states of the lower bit group data is z.
It becomes nK. In addition, the built-in signal processing circuit (is designed to prevent the input of the clock pulse P to the counter when the counter integrated value becomes zero and stop the counting operation). The mode signal indicating one of the operations when the operation is stopped is the lower phase signal θ6., and this lower phase signal ~ is i b
It becomes a logic signal of 1.0 of tt. The time ratio of this logic signal is the command phase signal θ. It is possible to obtain a lower phase signal which is PWM modulated proportionally to the lower bit group data. Further, the adder adds the upper phase signal aH and the lower phase signal θ4.0 to obtain the phase signal θ to the memory circuit (881), where the lower phase signal 04 (11)1 is sent to the memory circuit (881). Therefore, the phase signal θ is obtained as a value obtained by adding 0 to the upper phase signal σ.

FIG. 5 shows an explanatory diagram of the operation of the power supply command generator (6) having the configuration described above with respect to time changes.

In the figure, (a) * (b) is the command phase signal θ. to the upper bit group data. and lower pit group data σ,. , and the repetitive waveform part is approximated. (C) is Muyaria Vals P. , (d) is lower bit group data 0. .

, (Q) is the pulse width modulated T-phase signal #, % C
f) is the upper phase signal θyo and the lower phase signal θ6. The phase signal θ□, which is the sum of (g), indicates the digital power supply command signal obtained from the memory circuit ((a).
The function contents of the memory circuit (64I) are shown in Fig. 4 for the case of data 2, and the pulse width modulation part is shown by a dashed approximation line.
(The illusion is the digital power supply command signal, and the pulse width modulation part is shown by a dashed approximation line. Here, the '9. flow neutral point is set to zero when the digital power supply command signal is 8. In addition, in the configuration shown in Fig. 6, a D/mu converter is used to convert the digital power supply command (i. This analog power supply command signal V is obtained.

is almost the same as the AC ship's waveform shown by the approximate line in FIG. 5(i).

Therefore, according to the configuration shown in FIG. 3, it is possible to obtain a variable frequency power supply command signal whose frequency, amplitude, phase, and waveform can be arbitrarily selected as described above. Further, in order to improve the resolution of the phase signal and improve the waveform, it is better to increase the number of bits of the phase signal, but in this case, the capacity of the memory circuit inevitably increases. Therefore, in the case of the embodiment of the present invention, the phase signal θ subjected to pulse width modulation is
By setting □, the number of address inputs to the memory circuit is reduced, and the memory circuit capacity can be greatly reduced.

In the above embodiment, in order to obtain a multiphase power supply command signal, it is sufficient to prepare a memory circuit storing data of different phases, a D/A converter, and a harmonic removal filter for the number of phases. Of course, when obtaining a phase power supply command signal, a memory circuit, a DA converter, and a harmonic removal filter for two phases are prepared, and the remaining one phase can be easily obtained by analog addition of the other two phases. be.

As described above, according to the present invention, it is possible to obtain a variable phase power supply command signal, and also to easily change the frequency, amplitude, one phase, and waveform of the power supply command signal.

[Brief explanation of drawings]

Figure 1 is a block diagram of a general inverter, Figure 2 is a diagram of a conventional power supply command generator, Figure 6 is a diagram of a power supply command generator according to the present invention, and Figures 4 and 5 are respectively FIG. 3 is an explanatory diagram of the operation of the power supply command signal generator according to the present invention. (1)... Power converter T, ~T6-... Switching element (4)... Energization control circuit y, v, v... Power supply command signal su
sv aw (6)...Power supply command generator...Latch circuit ((321...IPWM modulator - 100 adder ((A)...memory circuit) function/D/A converter--Filter 1
``ao・φ Reference phase signal Po Association・Carrier pulse S・・Power supply control signal Pck・・Clock pulse θ,・・Phase signal θY・・Upper phase signal θ2・・Lower phase signal D・・Power supply command signal substitute People Makoto Kuzuno - Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] A latch circuit that takes in the upper bit group data of the input reference phase signal and obtains the upper phase signal in the power supply command generator of the power converter that supplies the power supply command signal to the energization control circuit that controls each switching element of the power converter. , a pulse width modulator that receives the lower bit group data of the reference phase signal as input and obtains a pulse width modulated upper phase signal; and a pulse width modulator that receives the lower bit group data of the reference phase signal and obtains a pulse width modulated upper phase signal; Adder to get the signal, and amplitude, phase,
The present invention is characterized by comprising a memory circuit which uses an input of a power supply control signal for selecting a waveform and a phase signal outputted from the adder as address inputs, and stores data of a power supply command signal corresponding to the address inputs. A power supply command generator for power conversion equipment.