JPS58221402A - Backup system of controller - Google Patents

Abstract

PURPOSE:To back up a fault of a controller by a manual operation when a trouble is generated in a processor of the controller, by executing the function of the processor for a processor of an interface and applying the contents stored in a memory to an operation center. CONSTITUTION:IF a trouble is generated in the processor CPUm of the controller CT, the function of the processor CPUm is executed by the processor CPUs of the interface and data corresponding to an analog output AO and a digital output DO from the operation center OS are applied to an I/O circuit I/Om. In addition, data indicating an analog input AI and a digital input DI from the I/O circuit I/Om are applied to the operation center OS. Being provided with an analog-to-digital converter, the I/O circuit I/Om repeats the operation to convert the analog input AI into a digital signal and store the converted digital signal once in a variable memory RAMm periodically and reads out the stored contents when necessary to apply them to the operation center OS.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a backup system for a controller used for process control and the like.

In recent years, controllers that perform control calculation operations using processors have become general-purpose, and the interface between them and the operation center that performs monitoring, control, etc. is relayed by an interface that also includes a processor, and at the operation center, It sends various data to the controller and monitors the various data sent from the controller, but if an abnormality occurs in the controller's processor, it will be unable to function as a controller and will be unable to operate. This also creates the disadvantage that monitoring and control at the center is not possible.

The present invention aims to fundamentally eliminate such drawbacks of the conventional technology, and focuses on providing a processor in the interface, so that when an abnormality occurs in the processor of the controller, the function of the controller is replaced by the processor of the interface. ,
It provides a backup method for the controller that exchanges digital input, analog output, and digital output data between the operation center and the input/output circuit, and also converts the analog input into a digital signal and stores it in memory once. The present invention provides a controller backup system in which the stored contents of the controller are provided to the operation center.

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 1 is a block diagram showing the configuration, and the controller CT is
Centered around the processor CPUm, fixed memory ROMm
, a variable memory RAMm and an input/output circuit t10m are arranged around the periphery, and these are connected by a bus BUSm, and the analog input A given from each sensor in the process is
I, while receiving the digital input DI via the input/output circuit l10m, the analog output AO is the result of the corresponding control calculation operation.

It is sent as a digital output Do to each actuator of the process via the input/output circuit l10m.

Note that the control operation is performed while the processor CPUrn executes instructions stored in the fixed memory ROMm and accesses necessary data to the variable memory RAMm.

In addition, a relay interface I/F is inserted between the bus line BUSm and the operation center O8, and this also
Centered on the processor CPU5, fixed memory ROM! l
I variable memory I) RAM5 and input/output circuit I10,
1 to Eka and 3 are arranged around the periphery, and these are connected by a bus line BUS g.

Note that a monitoring signal WDT indicating the occurrence of an abnormality in the processor CPUm is supplied from the monitoring circuit in the processor CPUm to the processor CPU5, and one processor CPU
U! Request signal RIQ sent when l occupies the right to use bus BUSm and response signal ACK thereto
are exchanged via input/output circuits I10 and I12.

Therefore, if an abnormality occurs in the processor CPUm, the processor CPU5 detects this using the monitoring signal WDT.
After executing the instruction in the fixed memory ROMg, the request signal RE is sent.
If the response signal ACK is obtained by sending Q, the processor CPUm is disconnected from the bus BU8m, the right to use BUSm is transferred to the processor CPU5, and the variable memory IJRA
The input/output circuit Δ addition is controlled by the processor CPU5 via the input/output circuit l10113.

That is, if an abnormality occurs in the processor CPUm, the processor CPU5 takes over the function of the processor CPU5,
Data corresponding to the analog output AO and digital output Do from the operation center O8 are given to the input/output circuit Δ addition, while data indicating the analog input AI and digital input DI from the input/output circuit l10m is supplied to the operation center O8.
It becomes something to give to.

However, the input/output circuit l10m includes an analog-to-digital converter (hereinafter referred to as ADC) that converts analog input AI to a digital signal, and a digital fist analog converter (hereinafter referred to as “ADC”) that converts the digital signal to analog output AO.
Since the conversion speed of the DAC and ADC is low, there is no particular problem with the analog output AOK, but the analog input AI is converted to a digital signal and then stored in the variable memory (I) RAMm at a cycle time. The stored contents are read out as necessary and then provided to the operation center OB.

Therefore, even if an abnormality occurs in the processor CPUm, the analog input AI and digital input DI can be monitored at the operation center O8, and the analog output AO and digital output Do can be freely controlled based on data from one operation center O8. Therefore, a failure in the controller CT can be backed up by manual operation of the operation center OS.

FIG. 2 is a flowchart showing the control situation of the processor cpvs corresponding to the first invention, and FIG. 3 is a flowchart showing the control situation of the processor CPUm corresponding to the first invention. 1 command reception to receive the command signal from sensor O8 is performed via the input/output circuit l10s1, and this is the Y of 7 reception complete?”
If it is ES, one read determines whether it is a read in which the operation center OS receives the digital input DI, or a write in which the data from the operation center O8 is sent out as an analog output AOi or a digital output DO? If it is YES, the monitoring signal M)T indicates whether the processor ``CPUm is normal?'' ”, and if this is ffs, the request signal RE
Q is sent to take possession of the right to use the bus line ``BUSm'', and the DII7- code is executed from the input/output circuit 7 l10n, and then the request signal 2 REQ is stopped to release the right to use the bus line ``BUSm''. Then, digital data "DI transmission" is performed to the operation center O8 via the input/output circuit l10sl.

However, if the processor "CPUm is normal?" is No, the input/output circuit "l10IT" is immediately disconnected because the processor CPUm has already been separated from the mother iJ BUSm.
Perform DI read from I.

Also, if "Read?" is NO, it is a write command, so in response to the YES of the processor "CPUm normal? °°", the variable memory I )” AO to RAMm.

DO is stored, the right to use the bus line "BUSm is released", and a confirmation signal "°" is sent to the operation center OS via the input/output circuit 11081.

However, if the processor "CPUm normal?" is NO, the input/output circuit "AOLDO write to l10m" is immediately executed.
Do the following.

In FIG. 3, the processor CPUm is connected to the operation center O.
Command from 8 to 6 light command? If the answer is YES, the processor ``CPUm self-check'' is performed by checking the control algorithm and status flag, and then ``Idle state?''. ” is YES, AO to input/output circuit 1■Δh
, Do write”.

4 to 6 correspond to the second invention,
FIG. 4 is a flowchart showing the periodic operation of processor CPU5, FIG. 5 is a flowchart showing interruptive operation of processor CPU1+, and FIG.
FIG. 4 is a flowchart showing the periodic operation of the CPU normal as described above. If this is YES, I would like to perform "occupy the right to use the mother f BU8m", then check the status flag of the variable memory "RAMm", and then release the right to use the bus "BUSm". "Decipher status flag", 1 idle to determine whether this is idle or processing state? ” to judge.

1 Idol? If ``is YES,'' the bus line ``BUSm'' is occupied, and the AD of the input/output circuit ``l10m'' is executed.
After carrying out "C start-up", "releasing the right to use BUSm" on the bus line, "waiting for a certain period of time" corresponding to the time required for ADC conversion, and after "occupying the right to use BUSm" on the bus line again, The input/output circuit ``takes in the ADC output of l10m'' and ``stores the output of the ADC in RAMm'', and performs ``release of the right to use the bus line BUSm''.

In addition, if "Idle?" is NO, the processor CP
When Um is in a processing state in which a control operation is being executed, the processor CPU 5 does not particularly execute a control operation.

Also, if the processor "CPUm normal?" is NO, the ADC of the input/output circuit "rlom" is activated immediately.

Wait for data time, take in ADC of input/output circuit 110m, and store ADC output in RAMm.

In FIG. 5, if "6 commands received from operation center O8" becomes YES in "1 reception completed?", 6 commands received from operation center O8? as in FIG. 2? If this is YES, is the processor “CPUm normal?” ”, and the result is Y.
At the time of ES, the bus line ""occupies the right to use BUSm", performs AI read from the variable memory "RAMm", performs the release of the right to use the bus line "BUSm", and sends the analog input "AI" to the operation center OS. ”

However, if the processor ``CPUm normal?'' is NO, the AI read from the variable memory ``RAMm'' will be performed immediately.

Note that if "Read?" is No, the same processing as in FIG. 2 is performed.

In FIG. 6, the processor CPUm is a variable memory
Check the status flag of RAMm, and
processing? If “ is YES, input/output circuit” I
``Starts up the ADC,'' performs ``taking in the ADC output of 110m'' and ``taking in the ADC output from the input/output circuit'' for a certain period of time, and ``stores the output of the ADC in RAFilh''.

Therefore, the analog input AI is converted into a digital signal by the ADC and then temporarily stored in the variable memory RAMm, and the contents are read out as necessary and transmitted to the operation center O8. It also becomes possible to monitor analog input AI.

However, the configuration in Figure 1 can be selected arbitrarily depending on the situation, and in Figures 2 to 6, unnecessary steps can be omitted or the order of each step can be changed depending on the conditions. However, the present invention is capable of various modifications.

As is clear from the above explanation, according to the present invention, when an abnormality occurs in the processor of the controller, manual operation is possible from the operation center, which has a remarkable effect on various process control devices. can get.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, FIG. 1 is a block diagram showing the configuration, FIGS. 2 and 3 are flowcharts of the control situation corresponding to the first invention, and FIGS. 4 to 6 are the second invention. 3 is a flowchart of the corresponding control situation. CT--controller, I/171--interface, OS @ operation center, CPUm, C
PU5... Φ Processor, RAIvir RAM5
e-...Variable memory, l10m, l10s 1~
Engineering 10I! I3...Input/output circuit, BUSm *
BUSs e * * m bus, AI@@*@...
・Analog input, DI...Digital input, AO・
・・Fist analog output, DO−・φ digital output, w
DT...Fist-monitoring signal, REQ...e-request signal, AC
K...Response signal. Patent applicant Yamatake Honeywell Co., Ltd. Agent Masaki Yamakawa (and one other person) Figure 2 Figure 3 Figure 5 Figure 6

Claims (2)

[Claims] (1) Control consisting of a controller that is equipped with a processor and an input/output circuit that handles digital input, analog output, and digital output and performs control calculation operations, and an interface that is equipped with a syrocessor and relays between the controller and the operation center. In this method, when the processor of the controller malfunctions, the processor of the interface takes over the function of the processor, and provides data corresponding to each of the outputs from the operation center to the input/output circuit, and A backup system for a controller, characterized in that data indicating the input from an input/output circuit is provided to the operation center. (2) A controller that includes a processor, memory, and an input/output circuit that handles analog input, digital input, analog output, and digital output, and performs control calculation operations; and a controller that includes a processor and relays between the controller and the operation center. In a control method comprising an interface, when a processor of the controller malfunctions, the processor of the interface takes over the functions of the processor, and sends data corresponding to each of the outputs from the operation center to the input/output circuit. and giving data indicating the digital input from the input/output circuit to the operation center;
A backup method for a controller, characterized in that data obtained by converting the analog input into a digital signal is stored in the memory, and the stored contents are provided to the operation center.