JPS58220486A - Manufacture of semiconductor light emitting element - Google Patents
Manufacture of semiconductor light emitting elementInfo
- Publication number
- JPS58220486A JPS58220486A JP10454882A JP10454882A JPS58220486A JP S58220486 A JPS58220486 A JP S58220486A JP 10454882 A JP10454882 A JP 10454882A JP 10454882 A JP10454882 A JP 10454882A JP S58220486 A JPS58220486 A JP S58220486A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- type inp
- substrate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
- H01S5/2237—Buried stripe structure with a non-planar active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/24—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a grooved structure, e.g. V-grooved, crescent active layer in groove, VSIS laser
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は半導体発光装置の製造方法に係り、特に、基板
に設けられたストライプ状の溝にレーザが発光する活性
領域が埋め込まれ九インジウム・ガリウム・ヒ索・リン
(InGaAsP) /インジウム・リン(Ink)系
ダブルへテロ接合型半導体レーザの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor light emitting device, and in particular, it relates to a method for manufacturing a semiconductor light emitting device. The present invention relates to a method for manufacturing a gallium-arsenic-phosphorous (InGaAsP)/indium-phosphorus (Ink)-based double heterojunction semiconductor laser.
(2)技術の背景
半導体レーザは他のレーザ系に比べて波長の選択が比較
的容易で且つ、小型、高効率動作、長寿命、^速直接変
病及び単一波長動作などの数々の利点があり、光伝送・
処理の各種の実用システムの光源として用いられてい゛
る。(2) Background of the technology Semiconductor lasers have many advantages such as relatively easy wavelength selection compared to other laser systems, small size, high efficiency operation, long life, fast direct deterioration, and single wavelength operation. There is optical transmission and
It is used as a light source in various practical processing systems.
特に、埋め込み構造を有する半導体レーザでrま、活性
領域の幅を実質上減少させ々ことができるので、1−値
電流を低減でき、且つ半導体レーザの各々端面での微分
量子効率全向上できるという効果がめる。In particular, it is possible to substantially reduce the width of the active region in a semiconductor laser having a buried structure, thereby reducing the one-value current and improving the differential quantum efficiency at each end facet of the semiconductor laser. See the effect.
(3)従来技術と問題点
第1図はIn’p基板にvsj−型の溝f:設け、該溝
中にInGaAsP活性層を埋め込んだ半導体レーザの
賛部断面図全示す。同図に於いて、1はnfi工nP基
板、2はp型InP層、3はn型工nPクラッド層、3
1は。型Ink層、番はInGaAsP活性層、5はp
型InPクラッド層、6はp側電極、7はn側電極上そ
れぞれ示す。(3) Prior Art and Problems FIG. 1 shows a complete cross-sectional view of a semiconductor laser in which a vsj-type groove f is formed in an In'p substrate and an InGaAsP active layer is buried in the groove. In the same figure, 1 is an NFI engineering nP substrate, 2 is a p-type InP layer, 3 is an n-type engineering nP cladding layer, 3
1 is. Type Ink layer, number is InGaAsP active layer, 5 is p
InP type cladding layer, 6 is shown on the p-side electrode, and 7 is shown on the n-side electrode, respectively.
この半導体レーザはp*Il’を極6に正、n側電極フ
に負の電圧全印加し、p型InP層2とn型In2層3
′のp−n逆″イア7によ・て・キパノアヲ一解内に埋
め込筐れた活性層4へ注入する。活性層4に注入された
キャリアは半導体層の接合に対して垂直方向vc隣接し
7tn製クツクラッド及びp臘りラッド層6にエリ、活
性層表内に閉じ込められる。そして十分な注入キャリア
によって利得が損失に打ち勝っm時、活性層番からレー
ザ光が生じる。In this semiconductor laser, a positive voltage of p*Il' is applied to the pole 6, a negative voltage is applied to the n-side electrode, and the p-type InP layer 2 and the n-type In2 layer 3 are
The carriers are injected into the active layer 4, which is embedded in the Kipano solution, through the p-n inverse diameter 7 of the current. The laser beam is confined within the surface of the active layer by the adjacent 7tn shoe cladding and p-type cladding layer 6. When the gain overcomes the loss due to sufficient injected carriers, laser light is generated from the active layer.
次に、第2図乃至第5図を参照して、上記構成から成る
半導体レーザの従来の製造方法の一部について説明する
。伺、第1図で説明し皮部分と同部分は同記号で指示し
である。Next, with reference to FIGS. 2 to 5, a part of a conventional method for manufacturing a semiconductor laser having the above structure will be described. The same parts as the skin parts explained in Fig. 1 are indicated by the same symbols.
第2図参照
(、l n型工nP基板1に液相エピタキシャル成長
法を用いてその表面にp型1nP層2會形成する0第3
図参照
(1)) 前記p型InP層2六面に二酸化シリコン
(Sin、)層8t−形成旨、、通常のフォト・エツチ
ング法會適用して5102層80ノ(ターニングを行な
い、溝形成用の窓9t−形成する。Refer to Fig. 2 (1) A p-type 1nP layer 2 is formed on the surface of the n-type nP substrate 1 using the liquid phase epitaxial growth method.
Refer to figure (1)) 8 layers of silicon dioxide (Sin) were formed on six sides of the p-type InP layer 2, and 80 layers of 5,102 layers were turned by applying a normal photo-etching method to form grooves. A window 9t is formed.
第4図参照
(0) ウェットエツチング法を適用し、4形成用の
窓9を介して基板lに達する深さのV*Uの溝lOを形
成する。Refer to FIG. 4 (0) A wet etching method is applied to form a groove 10 of V*U with a depth reaching the substrate 1 through the window 9 for forming 4.
id) #形成用のマスクとして使用し7’(810
□層8を除去する。id) #Used as a mask for formation 7' (810
□Remove layer 8.
第5図参照
(e) 液相エピタキシャル成長法を通用して、V字
型の溝10内にn型InPクラッド層3.InGaAs
P活性層番及びp m I n Pクラッド層5會順次
形成する。この時、n型工nPクラッド層3及びIn(
)aAaP活性層4は溝10内に埋め込まれるが、#1
0外部のp型InP12表面にもn型工n P 43’
及びInGaAgP層4′が成長する。また、レーザの
発光領域となる活性層4の断面は、中央部の厚さが厚く
、端部へいくに従って薄い所−三ケ月状となる。Refer to FIG. 5(e) An n-type InP cladding layer 3. InGaAs
A P active layer number and five p m I n P cladding layers are sequentially formed. At this time, the n-type nP cladding layer 3 and In(
) The aAaP active layer 4 is buried in the groove 10, but #1
0 There is also an n-type process on the external p-type InP12 surface n P 43'
And an InGaAgP layer 4' is grown. Further, the cross section of the active layer 4, which becomes the laser light emitting region, is thick at the center and becomes thinner toward the ends--a crescent shape.
上記の様な従来の製造方法では、n型工nPクラッド!
−3成味前にp型InP層2表面が一喝空気1
にさらされp壓InP層2の表面に汚染物が付着したり
、7字型の溝1 、Ot″形成る為に用いられたエツチ
ング液がp型InP層2の表面に残留し7tり。In the conventional manufacturing method as described above, n-type nP clad!
-3 The surface of the p-type InP layer 2 was exposed to a burst of air 1 before the formation, and contaminants were attached to the surface of the p-type InP layer 2, and it was used to form the figure-7 groove 1. The etching solution remained on the surface of the p-type InP layer 2 and amounted to 7 tons.
ま友、n m I EI Fクラッド層3の成長前の高
温保持のvlAp型工nPId2Nmからリン(P)が
昇華しfcりする等の問題が生じ、p型工uP層2とn
戯InP層3′との界面が良好なp −n接合が得られ
なか2′ft−0更に、n型工nP層3′の層厚は、n
fi工npり2ラド層3の層厚により決定されてしまう
為、例えばni工nPクラッド層3の一番厚いところで
の層厚Dμm)に対してn型InP層3′の層厚は約0
4(amlと薄く、pWInP層2とn型InPlii
3’間でブレークダウンが生じ易いという欠点かメ−)
り。Mayu, n m
Furthermore, the layer thickness of the n-type nP layer 3' is n
For example, the thickness of the n-type InP layer 3' is approximately 0 compared to the layer thickness Dμm at the thickest point of the Ni-type InP cladding layer 3 because it is determined by the layer thickness of the Ni-type InP layer 3.
4 (as thin as aml, pWInP layer 2 and n-type InPlii
Is it a disadvantage that breakdown is likely to occur between 3'?)
the law of nature.
(4)発明の目的
本発明は上記従来の問題点全解決し、電流狭窄機能とし
て十分なp −n接合半導体層全形成し、素子動作時に
ブレークダウンが生じることのない半導体発光素子の装
造方法全提供する。(4) Purpose of the Invention The present invention solves all of the above-mentioned conventional problems, and provides a semiconductor light emitting device in which a sufficient p-n junction semiconductor layer is formed as a current confinement function, and breakdown does not occur during device operation. All methods provided.
(5)発明の構成
本発明の上記の目的は、工nP基板上に第1の導′−型
を有するInP層、更に第2の導電型を有するInP層
金順次成長させ、該第2の導電型音響するInP7ii
i表面から前記InP基板に達する深さの凹部を選択的
に設け、該凹部に発光領域金膜ける仁とにより達成され
る。(5) Structure of the Invention The above object of the present invention is to sequentially grow an InP layer having a first conductivity type and a second InP layer having a second conductivity type on an engineered nP substrate. Conductive acoustic InP7ii
This is achieved by selectively providing a recess with a depth that reaches the InP substrate from the i-surface, and filling the recess with a light-emitting region gold film.
(6)発明の実施列
本発明の一実施例を第6図乃至第9図を参照して説明す
る。(6) Implementation of the Invention An embodiment of the present invention will be described with reference to FIGS. 6 to 9.
第6図参照
(、) スズ(Sn)がドープされたキャリア濃度が
2 x l O,’″〔副−1〕のn型工np基板11
に液相エピタキシャル成長法全適用してその表面にカド
ミウム(Cd)がドープされ几キャリア濃度が5 x
l O”(m−”)のp m I n P層12 ’f
r l(μm)の厚さに、更にSnがドープされたキャ
リア濃度が5 X 10 ”(m−’ )のn型工nP
層13i1(μm)の厚さに順次形成する。See FIG. 6 () N-type engineered np substrate 11 doped with tin (Sn) and having a carrier concentration of 2 x l O,''' [sub-1]
The surface was doped with cadmium (Cd) by applying the liquid phase epitaxial growth method, and the carrier concentration was 5 x
p m I n P layer 12 'f of l O''(m-'')
n-type nP with a carrier concentration of 5 x 10''(m-') and further doped with Sn to a thickness of r l (μm).
The layers 13i1 (μm) are sequentially formed to a thickness of 13i1 (μm).
第7図参照
(b) n型工nPH婦13にOVD法ま友はスパッ
タリング法を適用してその表面にSin、層14を30
00 (A)の厚さに形成する。Refer to Figure 7 (b) OVD method is applied to the n-type nPH layer 13 by sputtering to form a layer 14 of 30 nm on its surface.
00 (A) thickness.
(0) 通常のフォト・エツチング法を適用してst
O,414のパターニングを行ない、溝形成用の窓15
を形成する。同、この場合のエツチング液ハフッ化アン
モニウム(NH,iF)液t−使用する。(0) Applying the normal photo etching method
Patterning of O, 414 is performed to form a window 15 for forming a groove.
form. Similarly, in this case, an ammonium hafluoride (NH, iF) solution is used as the etching solution.
(d) ウェットエツチング法を適用し、溝形成用の
窓15−<介してng工nP基板11.piInP層1
2.及びn型工nP層13′t−エツチングし、幅約2
.5〔μm〕、深さ約35〔μm〕のV字型の溝16全
形証する。尚、この場合のエツチング液は体積比が塩酸
(HOt)ニリン(It (HA PO4) −3:
1の混合液を使用する。(d) Wet etching is applied to form a groove on the NG-etched nP substrate 11 through the window 15. piInP layer 1
2. and n-type nP layer 13't-etched to a width of about 2
.. 5 [μm] and a depth of approximately 35 [μm]. Note that the etching solution in this case has a volume ratio of hydrochloric acid (HOt) niline (It (HA PO4) -3:
Use a mixture of 1.
第8図参照
(、) 溝形成用のマスクとして使用し7’cSio
。Refer to Figure 8(,) 7'cSio is used as a mask for groove formation.
.
層14iNH,F液中に浸漬して除去する。Layer 14i is removed by immersing it in NH, F solution.
(f) i相エピタキシャル成長法金適用し、該V字
型の溝16にanがドープされたキャリア濃度が2 x
l O”(crn−” )、一番厚いところでの厚さ
が1.8[μm〕のndInPクラッド層1′I、ノン
ドープで一番厚いところでの厚さが017〔μm〕のI
nGaAsPffla層1B、Cdがドープされたキャ
リア濃度が5xlOI7(cm”)、一番厚いところで
の厚さが2.7〔μm〕の′p壓InPクラッド層19
を順次形成する。このとき、V字型の溝内の活性層18
の断面形状は、中央部の厚さが厚く、端部へいくに従っ
て薄い所副三ケ月状となる一方、n型InPld13表
面にも約05〔μm〕の厚さのn型InP層17′及び
厚さの薄いInGaABp層1 B’が順次成長する。(f) The i-phase epitaxial growth method is applied, and the carrier concentration of the V-shaped groove 16 doped with an is 2 x
l O"(crn-"), ndInP cladding layer 1'I with a thickness of 1.8 [μm] at its thickest point, I with a non-doped thickness of 0.17 [μm] at its thickest point
nGaAsPffla layer 1B, Cd-doped carrier concentration 5xlOI7 (cm"), 'p InP cladding layer 19 with a thickness of 2.7 [μm] at the thickest point.
are formed sequentially. At this time, the active layer 18 in the V-shaped groove
The cross-sectional shape of is thick at the center and becomes thinner toward the ends in a crescent shape, while the surface of the n-type InPld 13 also has an n-type InP layer 17' with a thickness of about 0.5 μm and a thick A thin InGaABp layer 1B' is successively grown.
(g) 更に続いて液相エビタキンヤル成長法ケ適用
し、p型工nPクラッド層19表面にcdがドープされ
たキャリア濃度がI X I O”(ctn−” )の
n戯InGaAsPキャップ層20を09〔μm〕の厚
さに形成する。(g) Subsequently, the liquid phase Evita kinial growth method is applied to form an n-type InGaAsP cap layer 20 doped with cd and having a carrier concentration of IXIO"(ctn-") on the surface of the p-type nP cladding layer 19. It is formed to a thickness of 0.09 [μm].
第9図参照
(h) 蒸着法を適用して、p型工nPキャップ層2
0表面に金(A u )/亜鉛(Z n)からgap側
電極21i3000(A)の厚さに形成し、そしてnf
iInP基板工1襄面に金(Au)/Snから成るn側
電極22i3000(A)の厚さに形成する。Refer to Fig. 9 (h) Apply the vapor deposition method to form a p-type nP cap layer 2.
A gap side electrode 21i of gold (A u )/zinc (Z n) is formed on the 0 surface to a thickness of 3000 (A), and nf
An n-side electrode 22 made of gold (Au)/Sn is formed to a thickness of 3000 (A) on the iInP substrate processing surface.
本実施例によれば、p −n接合半導体層、即ちp型I
np層12及びn型工nP層13會液相エピタキシャル
成長法によp連続的に成長させている為、p型InP層
12表面に於ける空気汚染、ウェットエツチング液の残
留及びPの昇華等が生じることなく、良好なp −n接
合界面を得ることができる。またn型工nP層13はブ
レークダウンが生じない厚さに制御できるので良好な素
子特性が得られる。According to this embodiment, the p-n junction semiconductor layer, that is, the p-type I
Since the np layer 12 and the n-type nP layer 13 are continuously grown using the liquid phase epitaxial growth method, air contamination on the surface of the p-type InP layer 12, residual wet etching solution, and sublimation of P are prevented. It is possible to obtain a good p-n junction interface without causing such occurrence. Furthermore, since the thickness of the n-type nP layer 13 can be controlled to a level that does not cause breakdown, good device characteristics can be obtained.
この様な方法で製作した半導体発光素子の1−値電流は
23(mA)、リークw、iは0−50(μA)であっ
た。伺、従来の製造方法で製作した素子の閾値電iは3
5〔mム〕、リーク電流はαl−5(mA)であった0
(7)発明の効果
本発明によれば、電流狭窄機能を有するp−n接合半導
体層上連続的に成長している為、良好なp −n接合界
面が得られ、良好な素子特性が得られるという効果がめ
る0The semiconductor light emitting device manufactured by this method had a 1-value current of 23 (mA) and leakage w and i of 0-50 (μA). The threshold voltage i of the device manufactured using the conventional manufacturing method is 3.
5 [mm], and the leakage current was αl-5 (mA). Therefore, it is possible to obtain a good p-n junction interface and obtain good device characteristics.
第1図は工nGaAsP/InP系埋め込み型半導体レ
ーザの要部断面図、第2図乃至第5図は従来の半導体レ
ーザの製造方法金示す工程断面図、第6図乃至第9図は
本発明の一実施例を示す工程断面図である。
1、li・・・n[工nP基板、2.12・・−pfi
InP層、3,17・・・n型工nPクラッドノー、3
’、13・・・nfiInP層、4.1B、、・工nG
aAsP活性/m、5゜19−−・p型InPクラッド
層、6.2l−p141t電極、第 1 図
消 2 図
第 4 図
第 S 図
躬6図
恥 7 図
第3図
男r図FIG. 1 is a cross-sectional view of essential parts of an embedded nGaAsP/InP semiconductor laser, FIGS. 2 to 5 are cross-sectional views of a conventional semiconductor laser manufacturing method, and FIGS. 6 to 9 are cross-sectional views of the present invention. It is a process sectional view showing one example. 1, lin...n[Engineering nP board, 2.12...-pfi
InP layer, 3, 17... n-type nP clad no, 3
', 13... nfiInP layer, 4.1B,... Eng nG
aAsP activity/m, 5゜19--p-type InP cladding layer, 6.2l-p141t electrode, Fig. 1 Fig. 2 Fig. 4 Fig. S Fig. 6 Fig. 7 Fig. 3 Male figure
Claims (1)
ウム・リン層、更に第2の導電型を有するインジウム・
リン層を順次成長させ、該第2の導電型金布するインジ
ウム・リン層弐面から前記インジウム・リン基板に達す
る深さの凹部を選択的に設け、該凹部に発光領域を設け
ること全特徴とする半導体発光素子の製造方法。An indium phosphide layer having a first conductivity type on the indium phosphide substrate, and an indium phosphide layer having a second conductivity type on the indium phosphide substrate.
A phosphorus layer is sequentially grown, a recessed portion having a depth reaching the indium-phosphorous substrate is selectively provided from the second surface of the indium-phosphorous layer covered with the second conductivity type metal layer, and a light-emitting region is provided in the recessed portion. A method for manufacturing a semiconductor light emitting device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10454882A JPS58220486A (en) | 1982-06-17 | 1982-06-17 | Manufacture of semiconductor light emitting element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10454882A JPS58220486A (en) | 1982-06-17 | 1982-06-17 | Manufacture of semiconductor light emitting element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58220486A true JPS58220486A (en) | 1983-12-22 |
Family
ID=14383525
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10454882A Pending JPS58220486A (en) | 1982-06-17 | 1982-06-17 | Manufacture of semiconductor light emitting element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58220486A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4758535A (en) * | 1986-05-31 | 1988-07-19 | Mitsubishi Denki Kabushiki Kaisha | Method for producing semiconductor laser |
US4824747A (en) * | 1985-10-21 | 1989-04-25 | General Electric Company | Method of forming a variable width channel |
US4837775A (en) * | 1985-10-21 | 1989-06-06 | General Electric Company | Electro-optic device having a laterally varying region |
US4845014A (en) * | 1985-10-21 | 1989-07-04 | Rca Corporation | Method of forming a channel |
US4966863A (en) * | 1988-07-20 | 1990-10-30 | Mitsubishi Denki Kabushiki Kaisha | Method for producing a semiconductor laser device |
-
1982
- 1982-06-17 JP JP10454882A patent/JPS58220486A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4824747A (en) * | 1985-10-21 | 1989-04-25 | General Electric Company | Method of forming a variable width channel |
US4837775A (en) * | 1985-10-21 | 1989-06-06 | General Electric Company | Electro-optic device having a laterally varying region |
US4845014A (en) * | 1985-10-21 | 1989-07-04 | Rca Corporation | Method of forming a channel |
US4758535A (en) * | 1986-05-31 | 1988-07-19 | Mitsubishi Denki Kabushiki Kaisha | Method for producing semiconductor laser |
US4966863A (en) * | 1988-07-20 | 1990-10-30 | Mitsubishi Denki Kabushiki Kaisha | Method for producing a semiconductor laser device |
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