JPS58220466A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To microminiaturize and accelerate a semiconductor device without deteriorating the characteristics by forming a semiconductor layer insularly on a sapphire substrate, adding an impurity, covering it with an insulating film as a wiring layer, covering it with a semiconductor layer, selectively removing it, and forming a polysilicon layer on the insular element forming region and the insulating film. CONSTITUTION:An epitaxial layer 12 is selectively formed on a sapphire substrate 11, ions are implanted to form an n<+> type layer 14, and covered with an SiO2 film 13. Then, an Si epitaxial layer 15 is superposed, ions are implanted as a p type layer, selectively etched to form a single crystal island 16 on the substrate and a polysilicon layer 17 on the film 13. Then, SiO2 films 18, 19 are covered, a polysilicon gate electrode 20 and a polysilicon wirings 21, and n<+> type layer 22 are formed, an SiO2 film is covered, windows are opened at the wiring layers 14, 17, 21 and the layer 22, aluminum wirings are attached to complete it. According to this configuration, multilayer wirings can be formed without causing the deterioration of the electric characteristics, ultrafinely and highly integrated device can be obtained, and a diffused wiring layer can be reduced in its resistance, thereby accelerating the element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that improves the separation technology of elements on an insulating substrate and the technology for forming wiring.

[Technical background of the invention]

Conventionally, the following methods have been known for element isolation and formation of a diffusion wiring layer in a semiconductor layer on an insulating substrate.

First, as shown in FIG. 1(a), for example, a sapphire substrate 1
5O8 (8111eonOn) on which a silicon semiconductor layer 2 with a thickness of 0.5 to 0.7 μm was epitaxially grown.
5apphi mae) Prepare ueno. Subsequently, a thermal oxide film 3 and a 515N4 film 4 are sequentially formed on the silicon semiconductor layer 2 (as shown in FIG. 1(b)). Continuing, 1st
As shown in FIG. Next, the stacked layer f-turn 5... is subjected to thermal oxidation treatment using the upper layer 815N4 film 4 as an oxidation-resistant mask to oxidize the remaining silicon semiconductor layer to be sawn out. Then, a field region 6 made of an oxide film is formed, and a plurality of island-shaped semiconductor layers 7 to be used as an element formation region and a diffusion wiring layer are formed (see FIG. 1).
e) As shown).

[Problems with background technology]

However, the above method has a number of drawbacks listed below.

(1) Since long-term high-temperature thermal oxidation is required, -At is auto-doped into the island-shaped semiconductor layer (device region, etc.) 7 separated from the sapphire substrate 1 (α-At 20 g) by the field region 6. As a result, electrical characteristics after device manufacture, particularly leakage current, increase. The increase in leakage current becomes a problem as a packed channel phenomenon when a MOS transistor is formed in the element region 7.

(2) During field oxidation, as shown in FIG. 1(e), the 81sN4 film 4 is tilted upward, and the stress causes defects on the surface of the multi-element region, deteriorating the electrical characteristics.

(3) Since field oxidation causes digging into the device region, so-called bird's beak, the effective width of the device region decreases, which in turn becomes an obstacle to miniaturization.

(4) When configuring a logic circuit or the like, a large number of diffusion wiring layers are used, which becomes an obstacle to increasing the degree of integration.

(5) In order to prevent the slope channel effect and mirror effect that accompany the shortening of the channel, the amount of doping of impurities used to form the north and drain regions is controlled to some extent. As a result, the resistance of the diffusion wiring layer formed at the same time cannot be reduced, which impedes the speeding up of the device.

[Purpose of the invention]

The present invention aims to provide a method for manufacturing a semiconductor device that can easily achieve miniaturization, high integration, and high speed without causing deterioration of the electrical characteristics of confectionery.

This semiconductor layer is selectively removed to form an island-shaped semiconductor layer, and impurities are added to this, and the layer surface is covered with an insulating film through oxidation treatment, etc., and the remaining island-shaped semiconductor layer is used as a diffusion wiring layer. Then, by forming a second semiconductor layer on the entire surface and selectively removing it, island-shaped element formation regions separated by the insulating film are formed on the sapphire substrate, and a polycrystalline semiconductor layer is formed on the insulating film. A second diffusion wiring layer is formed, each having two diffusion wiring layers, and further comprising a polycrystalline silicon wiring,
The main objective is to obtain a semiconductor device in which four-layer At wiring is possible and miniaturization can be achieved without causing deterioration of electrical characteristics.

[Embodiments of the invention]

Next, an example in which the present invention is applied to the manufacture of a MOS transistor will be described with reference to FIGS. 2(a) to 2(e).

(1) First, the thickness is 0.3~0.
Figure 2: Epitaxial growth of 7 μm first silicon layer (
a) As shown). Subsequently, an n-type impurity such as arsenic was ion-implanted into the island-like silicon layer 12 at a dose of 10"7cm2 to 10"10n20, and then thermal oxidation treatment was performed. At this time, the island-like silicon layer surface &C0・2μm
Thick oxide films 13 were grown on the front and back.

Note that the remaining n-type island-shaped silicon 7 layer 14 is used as a first diffusion wiring layer (as shown in FIG. 2(b)).

Grown epitaxially. At this time, sapphire substrate 1
A single-crystal silicon layer was formed on the substrate 1, and a polycrystalline silicon layer was formed on the other regions. Subsequently, a resist pattern (not shown) was formed on the polycrystalline silicon film portion on the oxide film 13, and using this as a mask, etching was performed using a polycrystalline silicon etchant. At this time, an element formation region 16 made of an island-like single crystal silicon layer separated by an oxide film 13 on the sapphire substrate 11 is formed into a second diffusion wiring layer I7 made of polycrystalline silicon on the oxide film 13.
... was formed (as shown in FIG. 2(d)). Note that in this step, when lowering the resistance of the second diffusion wiring layer 17, after growing the second silicon layer 15, a The impurities can be selectively doped using, for example, an ion implantation method using a T-lever.

0:i) Next, a thermal oxidation process is performed to form a 300 to 500X (71'-thick) oxide film 18 on the element forming region 16 and J knee, and around the second diffusion wiring layer 17... A second oxide film 19 of the same thickness was grown.Subsequently, a polycrystalline silicon film with a thickness of 2000 to 4000×, for example, was deposited on the entire surface and patterned to form element forming regions 16...
Dirt electricity on the gate oxide film 18! 2o..., the second
After completely forming the polycrystalline silicon wiring layer 21 on the second oxide film 19 of the diffusion wiring layer 17, e-) the electrode 2
o... etc. as a mask, n-type impurities, for example arsenic, are ion-implanted into the element forming regions 16... as source and drain regions. J! A region 22□... was formed (see Fig. 2). Then, a CVD-5io2 film (interlayer insulating film) was deposited on the entire surface according to a conventional method, and a second diffusion wiring layer was formed. 14..., 17..., contact holes are formed on the n+ type regions 22... and the polycrystalline silicon interconnection layer 21..., and then M vapor deposition and patterning are performed to form At interconnections. n-channel MO8LSI
was manufactured (not shown).

According to the method of the present invention, the island-like silicon layer 1 is prepared in advance.
2... and grown a thick first oxide film 13 on the surface thereof, a second silicon layer 75 is epitaxially grown, and the first oxide film 13 is formed on the sapphire substrate 11 by etching. An element forming region groove consisting of a separated island-like single crystal silicon layer is formed. Tsumaru, 2nd
After the growth of the silicon layer 15, the island-shaped element forming regions 16... are grown without any long-term thermal oxidation treatment at high temperatures.
can be formed. Therefore, auto-doping of AA from the sapphire substrate 11 to the element forming regions 16 can be eliminated, and the packed channel phenomenon can be prevented when the l-type regions 22 are formed as source and drain regions.

Furthermore, there is no reduction in the channel width due to bird beak, which is a problem with selective oxidation, and the r-) withstand voltage is also good, making it possible to achieve high reliability and miniaturization.

Furthermore, in the conventional method, the wiring layer consists of three layers: a diffusion wiring layer, a polycrystalline silicon wiring layer, and an At wiring layer. Since four wiring layers, including the wiring layer 17, the polycrystalline silicon wiring layer 21, and the AA wiring layer (not shown), can be realized, the degree of integration can be greatly improved. Moreover, the first diffusion wiring layer 14.
... is formed independently of the formation of the sheath and drain regions, and the amount of impurities added thereto is often limited, so that it is possible to achieve extremely low resistance and high speed.

In the above embodiment, the island-shaped semiconductor layer was covered with an oxide film formed by thermal oxidation, but the invention is not limited to this, and for example, CVD-81
It may be covered with 02 film or other insulating film.

In addition, in the above embodiment, the connection of each wiring layer and the connection with the source and drain regions were made using the At wiring layer through contact holes, but before epitaxially growing the second silicon layer, the first diffusion By selectively etching away a desired portion of the thick first oxide film on the wiring layer, the first diffusion wiring layer and the second diffusion wiring layer and the source and drain regions can be directly connected. If such a method is adopted, further miniaturization can be achieved.

In the above embodiment, an etching method was used to form the element formation region and wiring layer of the second silicon layer, but if planarization is a particular issue, a selective oxidation method may be used. Specifically, a thickness of 500 to 80 mm is deposited on the second silicon layer.
01@S 102 membrane and 2000-40001 g) 8i
sNaMf: Deposited and turned to form stacked layers and turns on the intended area of the element formation region and second diffusion wiring layer, and then thermally oxidized using this as a mask, and the thermal oxidation time In order to significantly shorten the time, using the laminated Noreen as a mask, oxygen is 1 (117/ItI~i o
``A method of performing heat treatment or thermal oxidation treatment after 7 cJ ion implantation is mentioned.

In the above embodiment, polycrystalline silicon was used as the f-)[pole, but the electrode is not limited to this, and may be formed of metal silicide, high melting point metal, or the like. The insulating substrate is not limited to sapphire, but also insulating substrates such as spinel, and S tO2-
Other dielectric separation plates such as polycrystalline silicon structures may also be used. The present invention is not limited to manufacturing n-channel MO8LSIs as in the above embodiments, but also applies to p-channel MO8LSIs, 0MOs, etc.
It can be similarly applied to 8LSI etc.

〔Effect of the invention〕

As described in detail above, the method for manufacturing a semiconductor device according to the present invention has remarkable effects such as excellent electrical characteristics and reliability, as well as the ability to achieve higher density and higher speed devices.

[Brief explanation of drawings]

Figures 1 (a) to (•) are cross-sectional views sequentially showing the steps of separating semiconductor layers on an insulating substrate and forming wiring layers by a conventional method, and Figures 2 (4) to (•) are Below are cross-sectional views sequentially showing the manufacturing process of n-channel MO8L8I in an embodiment of the present invention.

Claims (1)

[Claims] A step of forming a first semiconductor layer on an insulating substrate, a step of selectively removing this first semiconductor layer to form an island-shaped semiconductor layer, and a step of doping the island-shaped semiconductor layer with an impurity. , a step of covering the entire surface of the semiconductor layer with an insulating film, a step of forming a second semiconductor layer on the entire surface, and a step of forming the second semiconductor layer at least partially with the insulating film on the island-shaped semiconductor layer. 1. A method of manufacturing a semiconductor device, comprising the step of selectively removing so as to contact each other to form an island-like element formation region.