JPS58220465A - Writing and reading out method in floating gate type semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory which has no erroneous operation by reversing the relationship between a source and a drain in writing and reading out, thereby preventing the writing operation due to the read-out lasting for a long period of time even at a low wiring voltage. CONSTITUTION:In an avalanche injection type Nch non-volatile memory, the voltages of layers 2, 3 are set to V1>V2>0 at the writing time, a high positive voltage is applied to a control gate 6, and a hot electrons which are produced at the junction of a P type substrate 1 and an N<+> type layer 2 in a floating gate 5. A gate insulating film 4 in the vicinity of the layer 2 is locally reduced in thickness, and efficiently written with an electric field intensity increased even at the low wiring voltage. The voltage is set to 0<=V1<=V2 at the reading-out time, and a positive voltage is applied to the gate 6. A channel is formed on the surface of the substrate 1 under the gate 5 at this time, and since the voltage V1 is low, hot electrons are not almost produced at the P-N junction of the layer 2, a gate insulating film 4 is thick in the vicinity of the P-N junction of the layer 3, undesired writing hardly occur, and an erroneous operation due to writing in the reading-out state can be extremely reduced as compared with the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for writing and reading information in a floating gate semiconductor memory device.

This kind of conventional writing and reading method will be explained using an avalanche injection type N-channel nonvolatile memory device shown in FIG. 1 as an example. In the figure, (1) is a P-type semiconductor substrate as a first semiconductor region, and two N+ regions 2) and (3) are formed on the surface of this P-type semiconductor substrate (1) as second semiconductor regions. ) are provided spaced apart from each other, and a gate insulating film (4) is formed on the surface of the P-type semiconductor substrate (1) between the N regions (2) and (3).
A floating gate (5) and a control gate (6) are provided through the gate. Further, (1) is a field isolation insulating film.

In the above configuration, when writing information,
With the N region (2) as the drain, the applied voltage v1 is a positive high voltage, and with the N region (3) as the source, the applied voltage v2
A positive high voltage is applied to the control gate (6) with Ov or Vr>Vz. This allows the N region (2) under the floating gate (5) and the P type semiconductor substrate (1
) Hot electrons are generated at the PN junction between the control gate (6), and the hot electrons cross the potential barrier of the gate insulating film (4) and accumulate in the floating gate (5) due to the high voltage applied to the control gate (6). As a result, writing is performed. When reading, the N+ region (2) is used as a drain and the applied voltage v1 is a positive voltage □, and the N region (3) is used as a source and the applied voltage is set to 0 or a positive voltage such that vl>v2 to the control gate (6). Apply a positive voltage to At this time, a channel is formed on the surface of the P-type semiconductor substrate (1) under the floating gate (5), and an N region (
% 11 or 'θ' information can be read out depending on whether or not current flows from 2) to the N region (3) serving as a source.

Incidentally, in recent years, floating gate type non-volatile memory devices have become increasingly short-channeled, and the write voltage has also become lower as they become smaller, and memory devices that can write at lower and lower voltages will continue to be essential. There is a tendency to .

Yo. Uh, 8.4: Follow me. In the write and read method, write and read always drain one of the two N regions <2), (3).

The other is always the source, that is, the voltage V applied to both
Since the potential difference relationship between 1 + V 2 is always fixed as Vl > V2, as the writeable voltage decreases, even when reading is performed by applying a much lower voltage, as reading continues for a long time, The same thing as writing is performed, albeit little by little, and a problem arises in that a memory element that should not have been written becomes written into it and malfunctions.

This invention was made in view of the above-mentioned circumstances, and its purpose is to effectively prevent undesired writing from occurring due to long-term reading and causing malfunctions. An object of the present invention is to provide a method for writing and reading data in a floating gate semiconductor memory device.

In order to achieve such an object, the present invention provides a potential difference between two second semiconductor regions having a second conductivity type, which serve as a drain and a source, which are provided spaced apart from each other in a first semiconductor region having a first conductivity type. The relationship is reversed between writing and reading. That is, the second semiconductor region used as a drain during writing is used as a source during reading, and the second semiconductor region used as a source during writing is used as a drain during reading. The present invention will be described in detail below using the avalanche injection type N-channel nonvolatile memory device shown in FIG.

FIG. 2 is a cross-sectional view showing an avalanche injection type N-channel nonvolatile memory device similar to FIG. 1, and the same or corresponding parts as in FIG. 1 are indicated using the same symbols. However, the second
In the figure, the gate insulating film (4) near the N region (2)
) is locally thinned, but this has the effect of increasing the writing efficiency in which the N 2 region (2) is used as a drain and lowering the writing voltage, as will be described later.

Therefore, in the above configuration, when writing, the N region (2) is used as a drain and the applied voltage ■1 is a positive high voltage, and the N region (3) is used as a source and the voltage v
A high positive voltage is applied to the control gate (6) by setting 2 to O or a positive voltage such that Vl>V2.

As a result, hot electrons are generated at the PN junction between the N region (2) as a drain and the P-type semiconductor substrate (1), and these hot electrons are generated by the control gate (6).
) is injected and accumulated in the floating gate (5) over the potential barrier of the Sigut insulating film (4), and as a result, writing is performed as described above.
Here, since the gate insulating film (4) near the N region (2) is locally thinned, the electric field strength is large even at a lower write voltage than in the case of Fig. 1, allowing efficient writing. can be done.

Next, during reading, the N region (3) is used as a drain and the applied voltage v2 is a positive voltage, and the N region (2) is used as a source and the voltage v1 is controlled as Ov or a positive voltage such that Vl<V2.) (6) Apply K positive voltage. At this time, the P-type semiconductor substrate (
1) A channel is formed on the surface of N
Information on 11' or 10' can be read out depending on whether or not current flows from the + region 3) to the N+ region 2) as the source.
Since the applied voltage v1 and other voltages in region (2) are low, N
The probability that hot electrons will be generated at the PN junction between the region (2) and the P-type semiconductor substrate becomes extremely low, making it difficult to perform undesired writing. In addition, in the N region (3) as a drain, the N region (3) and the P type semiconductor substrate (
Since the gate insulating film (4) in the vicinity of the PN junction between the two electrodes (1) is relatively thick, the electric field for injecting hot electrons is weak, and undesired entrapment is unlikely to occur here as well.

Therefore, even with a long read operation, malfunctions due to writing in the read state are extremely reduced compared to the conventional case. That is, in the conventional case, for example, as described above, when the gate insulating film (4) is made thin in the vicinity of the N region (2) and the writing efficiency is increased by using the N region (2) as the drain, the read If a high voltage is applied using the original N 2 region (2) as the drain, hot electron injection will easily occur due to the large electric field strength.

In addition to the method of locally thinning the gate insulating film as described above, there are other methods to facilitate doping, such as locally increasing the amount of impurity ion doping in the channel region. A method can be used.

Further, in the above-described embodiments, only the case of an avalanche injection type N-channel nonvolatile memory device was explained, but the present invention is not limited to this, and the same effect can be applied even if it is applied to a P-channel nonvolatile memory device. It goes without saying that this effect can be obtained, and it may also be applied to other floating gate structure semiconductor memory devices, such as tunnel injection type non-volatile memory devices.As explained above, according to the present invention, writing and reading By reversing the source-drain relationship with
Even when the write voltage is lowered, it is possible to effectively prevent write operations associated with long-time reading, which has the excellent effect of providing a storage device with no malfunctions and high commercial reliability. .

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an example of a conventional floating gate type semiconductor memory device, and FIG. 2 is a sectional view of a floating gate type semiconductor memory device illustrating an embodiment of the present invention.・P-type semiconductor substrate, (2), (3)・
... N region, (4) ... gate insulating film, (5) ...
...Floating gate. Agent Makoto Kuzuno - Fig. 1 Fig. 2 Mr. Commissioner of the Japan Patent Office - Indication of the case Japanese Patent Application No. 57-105063 No. 2 Name of the invention Writing and reading method in a floating gate fast conductor memory device 3 Person making the amendment Relationship to the case Hitoshi Katayama, representative of the patent applicant, Department 4, Agent 5, Drawing subject to amendment 6, Contents of amendment Figures 1 and 2 of the drawings are amended as shown in the attached sheet. that's all

Claims (1)

[Claims] a first semiconductor region having a first conductivity type; two second semiconductor regions having a second conductivity type provided spaced apart on the surface of the first semiconductor region; and at least between these two second semiconductor regions. one of the conductor regions on the first semiconductor region is a drain;
A method for writing and reading in a floating gate semiconductor memory device, characterized in that the other semiconductor region is used as a source, and the second semiconductor region that is used as a source during writing is used as a drain, and the other is used as a source.