JPH0722194B2 - Non-volatile memory - Google Patents

Description

The present invention relates to a floating gate nonvolatile semiconductor memory having a MOS (Metal-Oxide-Semiconductor) structure.

Conventionally, in a non-volatile memory having a floating gate electrode, when a read voltage is applied to the drain of the non-volatile memory during a read operation of information (charge) written in the floating gate, the insulating film is formed by the voltage between the drain region and the floating gate electrode. Therefore, the charge may flow out from the floating gate electrode to deteriorate the memory retention characteristic of the nonvolatile memory. In particular, due to miniaturization of non-volatile memory devices and progress of lowering of program voltage, the insulating film under the floating gate electrode becomes thin as thin as a so-called tunnel insulating film in which a tunnel current flows due to a tunnel effect. in accordance with,
The risk of charge leakage during reading increases. Further, even if a surge voltage due to static electricity or the like is applied to the drain of the non-volatile memory from the outside, there is a drawback that the charge easily flows out from the floating gate electrode.

The present invention has been made to overcome the above-mentioned drawbacks, and provides a non-volatile memory having a structure in which charges are less likely to flow out from a floating gate electrode even when a voltage is applied to a drain region. is there.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 shows a sectional view of an embodiment in which the present invention is applied to a nonvolatile memory. In FIG. 1, 1 is a P-type substrate, 2 is a source region during reading, 3 is a drain region, that is, a region that operates as a reading region, 5 is a floating gate electrode, 6 is a control gate electrode, and 7 is an insulating film. is there. In the following 2 and 3, the names based on the time of reading the memory are used.
Reference numerals 20 and 30 denote extraction electrodes for the source region 2 and the drain region 3, respectively. Source region 2 and drain region 3
Are both formed of high-concentration n-type impurity regions, but a low-concentration n-type impurity region 35 is formed in the portion of the drain region 3 below the floating gate electrode 5. Except for the low-concentration n-type impurity region 35, FIG. 1 is the same as the well-known channel-implanted nonvolatile memory.
When electrons are injected into the floating gate electrode 5 (hereinafter referred to as a program), the minimum voltage to be applied to the control gate electrode 6 and the drain region 3 can be lowered as the thickness of the insulating film 7 becomes thinner. The insulating film 7 must be thinned not only to reduce the voltage required for programming, but also to reduce parasitic effects such as the short channel effect when the nonvolatile memory is miniaturized. For these reasons, when the insulating film 7 under the floating gate electrode 5 becomes thin and becomes about a tunnel insulating film, generally in a channel injection type non-volatile memory,
During the read operation, the voltage difference between the drain region 3 and the floating gate electrode 5 causes the floating gate electrode 5 to pass through the insulating film 7.
The risk of electron outflow from is increased. Particularly, when a large number of electrons are injected into the floating gate electrode 5 and the floating gate electrode 5 is negatively charged, and the channel under the floating gate is non-conducting, the read voltage is applied to the drain region 3 for reading. Is applied as it is, and a large voltage difference is generated between the floating gate electrode and the floating gate electrode which is negatively charged, and the possibility of outflow of electrons from the floating gate becomes extremely high. Even if such an electron outflow is slight, it will seriously affect the memory retention characteristics when the nonvolatile memory is used for a long period of time. However, in the nonvolatile memory of FIG. 1 according to the present invention, since the low concentration impurity region 35 is provided in the portion of the drain region 3 below the floating gate electrode 5, the floating gate electrode 5 is negatively charged, When a positive voltage is applied to the drain region 3, the voltage between the drain region 3 and the floating gate electrode 5 is a low concentration impurity region.
The depletion layer on the surface of 35 absorbs the voltage, and the voltage directly applied to the insulating film 7 is reduced.

FIGS. 2A and 2B show potential energy distributions with and without the low-concentration impurity region 35 in the drain region below the floating gate electrode. In the figure, C and V indicate band edges of the conduction band and the valence band, respectively. Second
FIG. 10A is a potential energy diagram in the case where the low concentration impurity region 35 according to the present invention is present. A large voltage is applied to the depletion layer of the low concentration impurity region 35, and the insulating film 7 is relatively small. Only voltage is applied. On the other hand, in the conventional case, as shown in FIG.
There is a high-concentration impurity drain region 3 instead of 32, and almost all the potential difference between the drain and the floating gate is applied to the insulator 7, and the thickness of the insulator is such that a tunnel current flows. When the thickness is reduced, that is, when the thickness is about the thickness of the tunnel insulating film, electrons easily flow out from the floating gate due to the tunnel effect or the like. Therefore,
If the impurity concentration of the low concentration impurity region 35 is not less than the degenerate concentration, the effect of reducing the voltage applied to the insulating film 7 is small.

As described above, the low-concentration region 35 of FIG. 1 makes it possible to obtain a non-volatile memory having excellent memory retention characteristics for read operations. However, this low-concentration impurity region 35 has a drawback that it increases the program voltage of the channel-implanted nonvolatile memory shown in FIG. This is because the low-concentration impurity region loosens the potential gradient in the depletion layer near the drain that generates photoelectrons during programming. In order to avoid this problem, it is necessary to devise a circuit so that the drain region 3 side is grounded and a program voltage is applied to the source region 2 during programming.

FIG. 3 shows another embodiment in which the above problem does not occur by applying the present invention. The only difference from FIG. 1 is that the select gate electrode 4 is inserted between the source region 2 and the floating gate electrode 5. In the nonvolatile memory of this structure, the generation of photoelectrons necessary for programming is not in the depletion layer near the drain region 3 but in the transition from the channel formed by the select gate electrode 4 to the channel formed by the floating gate electrode 5. Since it occurs near the point, the existence of the low concentration impurity region 35 does not affect the program voltage. To generate photoelectrons by this programming method, a voltage near the threshold of the select gate is applied to the select gate electrode 4 and a positive voltage is applied to the control gate electrode 6 and the drain with the source region grounded to the substrate 1. It becomes possible with. The minimum voltage to be applied to the control gate electrode 6 and the drain region 3 necessary for programming is the insulating film 7.
The film thickness can be reduced as the film thickness is reduced. In order to miniaturize, it is necessary to make the insulating film 7 thin for the same reason as in the nonvolatile memory of FIG. To read the charged state of the floating gate electrode 5 in the nonvolatile memory of this structure, a sufficiently high voltage is applied to the selection gate electrode 4 to make the channel under the selection gate conductive, and the control gate electrode 7 together with the source region 2 on the substrate 7 are connected. The conduction state of the channel under the floating gate electrode 5 when it is grounded is performed by applying a detection voltage to the drain region 3. Therefore, when the insulating film 7 under the floating gate electrode 5 is thinned, the risk of the outflow of charges from the floating gate electrode 5 at the time of reading increases if the low concentration impurity region 35 is not provided.
However, in the case where the low-concentration impurity region 35 is provided, stable characteristics in which the outflow of charges from the floating gate electrode 5 is unlikely to occur can be expected as in the description of FIG.

As described above, according to the present invention, it is possible to provide a non-volatile memory having excellent memory retention characteristics with respect to repeated read operations. Further, even when an unexpected surge voltage leaks to the drain region from the outside, it is possible to provide a nonvolatile semiconductor memory in which data accumulated in the floating gate electrode is less likely to be destroyed.

Although the semiconductor substrate has been described as the semiconductor region in which the nonvolatile memory is formed through the detailed description of the invention, this semiconductor region is a well region provided in the semiconductor substrate or an island formed on the insulating substrate. Needless to say, a semiconductor region having a rectangular shape is sufficient. In addition, although a non-volatile memory having a control gate electrode for controlling the potential of the floating gate electrode is taken as an example, the same effect can be obtained by applying the present invention to a memory without this control gate electrode. Of course.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of a nonvolatile semiconductor memory cell of the present invention, and FIG. 2 (a) is a potential distribution diagram from a floating gate to a drain region of a nonvolatile memory device according to the present invention, FIG. (B) is a potential distribution diagram from the floating gate to the drain region of the conventional memory device. FIG. 3 is a sectional view of another embodiment of the nonvolatile semiconductor memory cell of the present invention. DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate 2 ... High impurity concentration source region 3 ... High impurity concentration drain region (readout region) 4 ... Select gate electrode 5 ... Floating gate electrode 6 ... Control gate electrode 7 ... Insulating film 35 ... Low impurity concentration Drain region (readout region)

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 27/092 29/78 8934-4M H01L 27/08 321 E (72) Inventor Masaaki Kamiya Kameido, Koto-ku, Tokyo 6-31-1 Seiko Electronics Co., Ltd. (72) Inventor Yoshikazu Kojima 6-3-11-1 Kameido, Koto-ku, Tokyo Seiko Electronics Co., Ltd. (56) Reference JP-A-56-104473 ( JP, A)

Claims (3)

[Claims] 1. A semiconductor region of a first conductivity type, a read-out region of a second conductivity type different from the first conductivity type provided in a surface portion of the semiconductor region, and a tunnel insulation on the semiconductor region and the read-out region. A floating gate electrode provided via a film, and a surface portion of the read region which overlaps the floating gate electrode via the tunnel insulating film is depleted by electrons injected into the floating gate electrode. A non-volatile memory formed by a low-concentration region of two conductivity type. 2. The nonvolatile memory according to claim 1, wherein the impurity concentration of the low concentration impurity region is lower than the degenerate concentration. 3. A source region of the second conductivity type is provided on the surface of the semiconductor region away from the read region, and an insulating film is provided on the surface of the semiconductor region sandwiched by the floating gate electrode and the source region. The non-volatile memory according to claim 1, wherein a selection gate electrode is provided via the.