JPS58220178A - Graphic display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a graphic display device that receives graphic data from a computer and displays it.

Technical background A device that receives data such as figures, characters, symbols (herein simply referred to as figures) from a computer and displays it on a CRT screen is connected to a computer (not shown) as shown in Figure 1. order control unit 1o, vector generator 12, positioning circuit 14, graphic memory 16, display control unit 1
8, equipped with a CRT 20, a character generator 22, etc., a triangular shape,
When displaying figures such as rectangles, calculate their corner points Pi from a calculator.
X.

The Y coordinates xi and 'y't are sent to the order control unit 1.
0 is given to the vector generator 12, which generates a line segment connecting P+ (X+, Y+) and P2 (XI Y2), a line segment connecting P2 (X2., Y2) and P3 (XiY3), etc. and writes it into the graphic memory 16. The graphic memory 16 is a memory compatible with the CRT 20 screen.
Specifically, the number of memory cells corresponding to each pixel on the screen is the number of horizontal scanning lines times the number of pixels per horizontal scanning edge.

The display control unit 18 repeatedly reads this data in synchronization with the scanning of the CRT, and changes the brightness depending on the read data.
Graphics such as triangles and squares written in the graphic memory are displayed on the screen. The character code and display position information are sent from the computer, and then the character generator 2
2 generates a character pattern, and the positioning circuit generates display position coordinates, the latter is an address, the former is written as data to the graphic memory 16, and is read out in synchronization with scanning and displayed on the CRT 20 by making it a brightness modulation signal. be done.

Prior art and problems This kind of graphic display device is CAD (Computer
When used in the field of aided design, etc., there is a demand for drawing figures on the surface of a CRT tube in the form of graph paper, and in this way the operator can immediately read the dimensions, position, etc. of the figure from the grid. It has the advantage that it can be easily normalized, and is much easier to handle than drawing figures on a blank sheet of paper because there is no grid. Especially when designing printed circuit boards, integrated circuits, etc. using the grid method, grid points are essential.

However, in conventional graphic display devices, the graphic generator is a vector generator (there is also a circular graphic generator), so grids must be created using a vector generator, and with this, data input from a computer cannot be generated. The amount is huge. In other words, if the screen consists of 1024 x 1024 pixels, 8
Even if one grid point (intersection point) is added to each pixel, there are 128 x 128 points, and the computer calculates the X of each of those points,
You have to enter the Y coordinate, and it takes several tens of seconds for line-connected devices.
It takes a long time, such as more than a second.

OBJECT OF THE INVENTION The present invention aims to improve the above points, by providing a grid point generator inside a graphic display device, and simply by receiving pitch data, grid points (grid points, that is, points at each intersection of the grids) are displayed on the screen. (but not line segments). The number of pixels that make up a CRT screen cannot be increased too much due to resolution (even if you increase it, it would be meaningless as it would be crushed), and standard CRTs have 100OX.
The limit is about 1000. There are a variety of grids drawn on this, from those with fine intervals such as one every three pixels to those with coarse intervals such as one every 10 or 100 pixels, and of course there may be cases where it is not divisible and results in a fraction.

Another object of the present invention is to arrange all the squares at as equal a pitch as possible even in the case of fractional numbers.

Structure of the Invention The present invention comprises a circuit that receives graphic data from a computer and generates a graphic pattern in accordance with the graphic data, a graphic memory into which the graphic pattern is written, and a display section that receives readout output from the memory and displays the graphic. In the device equipped with,
It is characterized by comprising a lattice point generation circuit which receives accurate data including decimal points indicating the pitch of lattice points and the start and end coordinates of the display area from the computer and outputs the coordinates of each lattice point within the display area. However, this will now be explained with reference to examples.

In FIG. 1, 24 is a lattice point generation circuit provided in the present invention,
The details are shown in Figure 2. When generating lattice points, the computer sends the pitch ΔX in the X direction and the pitch ΔY in the Y direction of the lattice points. 26°28 in Figure 2 is these ΔX, ΔY
is the register that is set. In addition to drawing the grid on the entire screen, (7) it is also desirable to draw it only on a part of the screen, so the coordinates of the upper left corner specifying the area where the grid exists
I, Y construction and lower right corner coordinates X2. Y2 is also sent from the computer.

30, 32, 34, and 36 are registers in which these coordinate values are set. 38.40 is the selection circuit, 42.44
is an adder, 46.48 is a comparator, 50°52.54 is an AND gate, 56 is an OR gate, 58.60.62.6
4 is a latch (register).

From the computer, obtain the horizontal pitch ΔX, vertical pitch ΔY9, the upper left corner coordinates of the display area XI, Y1. When the lower right coordinate X2°Y2 is sent to the registers 26.2B, 30, 32, 34°36 and the start signal ST is input to the OR gate 56, the OR gate produces an output, and the output is connected to the a input terminal of the selection circuit 38. to go into. When there is this input, the selection circuit 38 selects the A input,
Lunch 58.60 takes it. As shown in the figure, one of the A inputs is O1 and the other is Xl, so the contents of the latches 58 and 60 are 0. Becomes XI. Adder 42 outputs X1+0=Xt, which becomes the memory's X address. Comparator 46
compares the output X of the adder 42 and the content X2 of the register 34, and opens AND gates 50 and 54 if X≦X2. Therefore, when the timing signal T2 is input, the AND gate 50 produces an output, which becomes a signal instructing the memory to write. Also, when the start signal ST is input, the selection circuit 40
is A input 0. Select Yl, these are lunch 62.64
The adder 44 outputs 0+Y1-Yl, which becomes the memory's X address.

Although not shown, the write data is "1" or "0" that indicates the grid point. In this example, it is "1", and therefore the memory 16 (
In Figure 1), the word and column addresses are Xi, Yl.
"1" is written into the memory cell of.

Next, at timing T1, a pulse enters the AND gates 52 and 54, and since the gates 54 are open, the selection circuit 38
The selection circuit 38 selects the B input. B input is ΔX of register 26 and output X of adder 42
, here Xl, and the adder 42 adds these and outputs X=Xl+ΔX. If X1+ΔX<X2, the comparator 46 opens the gate 50.54, and a write pulse W is output at timing T2. The same goes for the rest, and in this way, lattice points "1" are written one after another in the memory 1.6 at a pitch of ΔX in the X direction. ΔX input from the computer is
For example, when drawing grid points divided into seven equal parts at horizontal 13c+n, ΔX=13/7=1.8571428... However, the data should be as detailed as possible, including the decimal places. In this way, lattice points can be generated at substantially uniform pitches, although underflow may occur in an adder or the like, resulting in slight differences in the minimum digit of each pitch. Note that lattice points occur only in integer parts corresponding to memory cells or pixels, and fractions are used for calculations. Fractions in the calculation result may be rounded off instead of being rounded down.

Comparator 46 does not open AND gates 50 and 54 when X=X1+nΔX>X2, but instead opens AND gate 52. Therefore, writing is not performed to the memory cell at this X address, and instead, when the timing pulse of T1 is input,
AND gate 52 and therefore OR gate 56 produce an output, and selection circuit 38 has A inputs 0. Select Xl. Therefore, the output of adder 42 returns to the original Xl. The output of the AND gate 52 is input to the b input of the selection circuit 40, causing the selection circuit to select the B input .DELTA.Y and the output Y of the adder 44 (here <Yl as described above). Therefore, the adder 44 is Y1+Δ
Outputs Y, which becomes the memory's X address. Therefore, this time the Y address of memory 16 is Yl +AY,X7
Flz is XI, X1+ΔX, X1+2ΔX,...
Grid points "■" are written to the memory cells of . The same goes for the following, and the comparator 48 compares the X address output by the adder 44 with the content Y2 of the register 36, and
>2, a signal END indicating the end of memory writing is output. The time required to write grid points to this memory is
For example, it only takes 1 second compared to 2 minutes in the conventional method.

In the conventional method, a vector generator 12 is used to generate grid points. Line segment generation is performed by giving start and end point coordinates as described above, but lattice points (lit spots) are generated by giving the same start and end point coordinates. Therefore 100 x 100
= 2000(1) to generate 10000 grid points
It is necessary to input X and Y coordinate values, and if accurate values including fractions (below the decimal point) are used for each coordinate value, the total amount of data is ``huge''.
It must be transmitted through a communication speed line such as PS. In this regard, in the present invention, the required data are ΔX and ΔY, and for specifying the display area (Xl, Yl), (X2.
Even if Y2) is used, only 6 pieces are required.

If the screen is 1024×1024 pixels, 1024=
2, and since the pitch is the smallest when all pixels are used as grid points, 10 bits are sufficient for coordinate display.

This is a case where the coordinates can be expressed as an integer, but if it includes a fraction, then if 10 bits are assigned to it, the coordinate value will have 2 bits.
It is necessary to prepare a 0 bit. Generally, 2 bytes are often used for one coordinate value, and 4 bytes are used for displaying one point.

There are several ways to generate vectors, one of which is
One method is to use gradients. That is, the starting point is Xi, Y
l, the end point is X2. If Y2, the slope α is α=ΔY/ΔX=
(Y2-Yl)/(X2-Xi), so X is Xi
, X1+1. X1+2. When incremented, Y becomes Yl, Yl+α.

0 Y1+2α,... This α, 2α,...
Check whether ... is 1, 2, etc., and round down the fractions to Yl, Yl, Yl-1-1, ...
...and so on. Since it is troublesome to divide ΔY/ΔX, it is common to multiply by ΔX and check whether ΔY, 2ΔY, . . . . In case of lattice point generation, ΔY - ΔX
-0, and simply plots the starting and ending points.

Moreover, when a grid is represented by a large number of grid points, there is an advantage that the figure is not difficult to see or is not misunderstood, compared to a case where the grid is represented by a large number of vertical lines and horizontal lines.

Furthermore, instead of writing the lattice points generated by the lattice point generation circuit 24 into the graphic memory 16, if a lattice point memory is prepared and written therein, and then read out together with the graphic memory in synchronization with the scanning of the CRT, the screen Even if you erase the upper graphic pattern, the grid points remain, giving you the same feel as using graph paper.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, grid points can be accurately generated on desired beaches and in desired regions with a small amount of data from a computer, which is extremely effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of the present invention, and FIG. 2 is a block diagram showing details of a lattice point generation circuit. In the drawing, 12 is a circuit for generating a graphic pattern, 16 is a graphic memory, 20 is a display section, and 24 is a lattice point generating circuit. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi 1 2 Figure 2

Claims (1)

[Claims] An apparatus comprising: a circuit that receives graphic data from a computer and generates a graphic pattern residue according to the graphic data; a graphic memory into which the graphic pattern is written; and a display section that receives read output from the memory and displays the graphic. A figure characterized by comprising a lattice point generation circuit which receives accurate data including decimal points indicating the pitch of lattice points and the start and end coordinates of a display area and outputs the coordinates of each lattice point within the display area. Display device.