JPS5821839A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5821839A JPS5821839A JP56121154A JP12115481A JPS5821839A JP S5821839 A JPS5821839 A JP S5821839A JP 56121154 A JP56121154 A JP 56121154A JP 12115481 A JP12115481 A JP 12115481A JP S5821839 A JPS5821839 A JP S5821839A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- chip
- polycrystalline silicon
- silicon layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に係シ、特に半導体装置のウェハー
状態での直流検査およびフ了ンクシ、ン検査すなわちウ
ェノ・−試験の判定結果をチップ毎に電気的に曹き込み
、後工程でその結果を電気的に読み出す事？可能にした
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and in particular, to electrically detecting the judgment results of a DC test and a wafer test of a semiconductor device on a chip-by-chip basis. Is it possible to read out the results electrically in the subsequent process? This article relates to a semiconductor device that has made this possible.
従来のウェハー試験では、チップ毎に良品か不良品かを
判定し、不良の場合、チップ表面に機械的にキズ全村け
ているので、良品と不良の二種類にしか分類できず、ス
ピードグレード分類等を含む三種類以上の分類に不可能
であった。またチップ表面にキズ１付けるため、例えば
試験装置の故障等により良品が誤って不良と判定された
場合、良品は完全に破壊され、再び６（１」足會行って
良品を選別する串ができないという欠点があった。さら
に、ダイシング後の良品チップの選別は目視により行っ
ているため作業の自動化が困難であるという欠点もある
。In conventional wafer testing, each chip is determined to be good or defective, and if it is defective, all the scratches are mechanically removed on the chip surface, so it can only be classified into two types: good and defective, and the speed grade It was impossible to classify more than three types, including classification. In addition, since a single scratch is created on the chip surface, if a good product is mistakenly determined to be defective due to a malfunction in the testing equipment, for example, the good product will be completely destroyed and it will not be possible to perform another 6(1) visit to sort out the good products. Furthermore, since good chips are selected visually after dicing, it is difficult to automate the process.
本発明は、半導体装置のチップ内部に筒抵抗の多結晶シ
リコン層を介してシリコン基板と電気的に接続される全
域電極？’ｌ＝＋するテストデバイスを設ける＃により
、上記の！うな欠点を取り除き、生産性の扁い半導体装
置を提供する事を目的としている。The present invention provides a wide area electrode that is electrically connected to a silicon substrate through a polycrystalline silicon layer of a cylindrical resistor inside a chip of a semiconductor device. 'l = + by # providing a test device, the above! The purpose is to eliminate these drawbacks and provide a semiconductor device with low productivity.
次にこの発明の特徴を良く理解するために、その実施例
を第１図および第２図を用いて説明する。Next, in order to better understand the characteristics of the present invention, an embodiment thereof will be described with reference to FIGS. 1 and 2.
第１図に示すようにシリコン基板１上のフィールド絶縁
膜２を開孔したコンタクト孔３により、高抵抗多結晶シ
リコン層４を介して、シリコン基板と電気的に接続され
る金属電極５をチップ内に形成する。高抵抗多結晶シリ
コンは第２図に示すように、一定レベル以上の電圧を印
加すると否可逆的に抵抗値が変化する。例えば面積が１
００μｎ−１厚さ１．０μｍの高抵抗多結晶シリコン層
に対し、１０Ｖ以上の電圧７１ｉｌ−１，，０μ３の時
間印加する事によシ、抵抗値を１×１０７Ω・ｃｍから
１． Ｘ １０’Ω・備まで約３桁低下させるη１がで
きる。As shown in FIG. 1, a metal electrode 5 is connected electrically to the silicon substrate through a high-resistance polycrystalline silicon layer 4 through a contact hole 3 formed in a field insulating film 2 on a silicon substrate 1. form within. As shown in FIG. 2, the resistance value of high-resistance polycrystalline silicon irreversibly changes when a voltage of a certain level or higher is applied. For example, the area is 1
By applying a voltage of 10 V or higher to a high-resistance polycrystalline silicon layer with a thickness of 1.0 μm for a time of 71 il-1, 0 μ3, the resistance value changes from 1×10 7 Ω·cm to 1.0 μm. It is possible to reduce η1 by about three orders of magnitude to X 10'Ω.
高抵抗多結晶シリコンには、このような性質があるため
、例えばウェハー試験時に、一つのチップの試験が完了
し、不良であった場合、試験装置から電極６に電ＥＥを
印加し、良品であった場合電Ｉｆを印加しなければ、チ
ップの良、不良の悄＠をチップ毎に電気的に書き込む事
が可能となり、ダイシング工程後、分離されたチップに
ついて、基板と金員′亀イタ５の曲に電流を流し、抵抗
全測定すればチップの良、不良を電気的ＫｄＣみ出す事
ができる。すなわち、このようなテストデバイスをチッ
プ内に設ける事により、ウェハー試験の際、チップ表面
にキズケ付けずに良品、不良の５）−類する躯が０ｆＦ
ｒピになり、試Ｌ４装置の故障等による良品の破壊を防
ぐ事がでさ、また、ダイシング俊の良品チップ選別の自
動化（ｉ−各局にできる。さらにこのテストデバイス２
チツプ内Ｋ ｒＭ 数個収ける事により、スピードグレ
ード分類等圧＊Ｍｉ Ｍ以上のチップ分類を行うｕｌが
可能となる。Because high-resistance polycrystalline silicon has such properties, for example, during wafer testing, if one chip is tested and found to be defective, an electric current EE is applied to the electrode 6 from the test equipment, and it is determined whether the chip is good or not. If the electric current If is not applied, it becomes possible to electrically write the status of the chip whether it is good or bad for each chip. By passing a current through the curve and measuring the total resistance, you can find out whether the chip is good or bad by electrical KdC. In other words, by providing such a test device in the chip, during wafer testing, it is possible to determine whether the chip is good or defective without scratching the chip surface.
It is possible to prevent the destruction of non-defective chips due to failure of the test L4 equipment, etc., and to automate the selection of non-defective chips for quick dicing (i-can be done at each station.Furthermore, this test device 2
By accommodating several K rM in a chip, it becomes possible to classify chips of equal pressure*Mi M or higher for speed grade classification.
なお、このテストデバイスは半導体装置本体の製造プロ
セスヲ経て形成されるため、プロセスによっては、第３
図のように篩抵抗多結晶シリコン層１４とシリコン基板
１１の間に不純！吻ドープさ几たシリコン及、仮と同一
２ｈ電型の低抵多結晶シリコン層１６全形成し、金Ｖ４
箪極１５と昼俳抗多結晶シ１ノコンノ曽１４の間に前ｄ
α低抵多結晶シリコン層１７を形成する構造にしても良
い。Note that this test device is formed through the manufacturing process of the semiconductor device itself, so depending on the process, the third
As shown in the figure, there is an impurity between the sieve resistance polycrystalline silicon layer 14 and the silicon substrate 11! A low-resistance polycrystalline silicon layer 16 of the same 2h type as the temporary doped silicon layer 16 is formed, and a gold V4 layer is formed.
Front d between Kanogoku 15 and Hiruhaitan Polycrystalline Shi1nokonnoso 14
A structure in which the α low resistance polycrystalline silicon layer 17 is formed may also be used.
以上説明したように、本発明によれば、生産性の良い半
導体装置が容易に製作できる。As described above, according to the present invention, a semiconductor device with high productivity can be easily manufactured.
第１図（ａ）は本発明の第１の実施例によるテストデバ
イス構造の正面図、第１図（ｂ）は第１図（ａ）の−魚
頭線部分における断面図、第２図は高抵抗多結晶シリコ
ン層の電圧電流特注全示した図、第３図は本発明の第２
の実施例によるテストデバイス構造の断面図である。
なお図において、１．１１・・・シリコン基板、２゜１
２・・・フィールド絶縁膜、３．１３・・・コンタクト
孔、４．１４・・・高抵抗多結晶シリコン層、５．１５
・・・金属電極、１６．１７・・・低抵抗多結晶シリコ
ン層、である。
代理人 弁理士 内 原 晋５−
翁２図FIG. 1(a) is a front view of the test device structure according to the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along the -fish head line in FIG. 1(a), and FIG. Figure 3 shows the voltage and current customization of the high-resistance polycrystalline silicon layer.
FIG. 3 is a cross-sectional view of a test device structure according to an embodiment. In the figure, 1.11...silicon substrate, 2゜1
2... Field insulating film, 3.13... Contact hole, 4.14... High resistance polycrystalline silicon layer, 5.15
...Metal electrode, 16.17...Low resistance polycrystalline silicon layer. Agent Patent Attorney Susumu Uchihara 5- Old Man 2
Claims (2)
と電気的に接続される金属電極を有するテストデバイス
をチップ内に含む事を特徴とする半導体装置。(1) A semiconductor device characterized in that a chip includes a test device having a metal electrode electrically connected to a silicon substrate via a high-resistance polycrystalline silicon layer.
び金属電極と前記高抵抗多結晶シリコン層の間に、不純
物ドープされたシリコン基板と同一導電型の低抵抗多結
晶シリコン層を有する特許請求の範囲第（１）項記載の
半導体装置。(2) A patent claim that includes a low-resistance polycrystalline silicon layer doped with impurities and having the same conductivity type as the silicon substrate between the high-resistance polycrystalline silicon layer and the silicon substrate and between the metal electrode and the high-resistance polycrystalline silicon layer. The semiconductor device according to scope (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56121154A JPS5821839A (en) | 1981-07-31 | 1981-07-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56121154A JPS5821839A (en) | 1981-07-31 | 1981-07-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5821839A true JPS5821839A (en) | 1983-02-08 |
| JPS6157700B2 JPS6157700B2 (en) | 1986-12-08 |
Family
ID=14804181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56121154A Granted JPS5821839A (en) | 1981-07-31 | 1981-07-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821839A (en) |
-
1981
- 1981-07-31 JP JP56121154A patent/JPS5821839A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6157700B2 (en) | 1986-12-08 |
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