JPS58216971A - Apparatus for automatically tracking loran c signal - Google Patents

Abstract

PURPOSE:To carry out the phase synchronism of a LORAN C signal and a synchronous pulse even if the receiving state of the LORAN C signal is relatively unstable, by carrying out phase synchronism even at a four-cycle position when phase synchronism at a three-cycle position is unstable. CONSTITUTION:When a synchronous pulse b1 is subjected to phase synchronism at the three-cycle position P3 of a LORAN C signal, a sampling circuits 7A carries out the sampling of the point Q1 of the LORAN C signal by a S/N detecting pulse C1. By this operation, the synchronous pulse b1 is sent out from a change- over circuit 5 by a logic circuit 6 and the phase synchronism at the position P3 of the LORAN C signal is held. When the S/N ratio of the LORAN C signal becomes bad and phase synchronism becomes unstable, for example, a synchronous pulse b2 is sent out to the circuit 5 by a judgement device 10B and phase synchronism is carried out. When the pulse C1 is stabilized, the phase synchronism by the pulse b1 is again carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for tracking a specific phase of a Loran C signal.

As is well known, the Loran C signal is formed by pulse modulating a 100KH2 carrier wave, and the Loran C receiver synchronizes the synchronization pulse generated inside the receiver with a specific phase of the pulse modulated carrier wave. ing. As is well known, this specific phase is set at the third cycle position of the carrier wave at the rising edge of the Loran pulse, taking into consideration the S/N ratio of the signal, the influence of spatial waves, etc.

The synchronization between the Loran C signal and the synchronization pulse is affected by the S/N ratio of the Loran C signal. For example, if the S/N ratio is extremely poor at a long distance position, synchronization at the third cycle position cannot be maintained. .

By the way, the amplitude of the Loran C carrier wave gradually increases according to the envelope at the rise of the pulse modulated wave.

Therefore, even if the perspective ratio of the Loran C signal is relatively poor, synchronization may not be possible at the 3rd cycle position because the amplitude of the carrier wave is relatively wide at the 4th or 5th cycle position of the Loran C carrier wave. However, synchronization is possible at the fourth or fifth cycle position.

Based on the above, when the S/N ratio of the Loran C signal deteriorates beyond a certain level, the synchronization accuracy slightly deteriorates, but the synchronization position of the synchronization pulse is changed to the fourth or fifth cycle.
The synchronization position is changed to the cycle position and a synchronization operation is performed, and when the S/N ratio returns to a good state, the synchronization position is returned to the third cycle position. Furthermore, we have realized a device that can automatically change the synchronization position from the 3rd cycle position to the 4th or 5th cycle position, and return to the 3rd cycle position, etc., depending on the S/N ratio of the Loran C signal. do.

The present invention will be explained below based on embodiments.

In Fig. 1, reference numeral 1 denotes a reference pulse train sending circuit that sends out a reference high-frequency pulse train. The frequency is divided. The pulse train frequency-divided by the frequency divider circuit 2 is sent to the synchronization pulse generation circuit 3 to generate synchronization pulses.

The synchronous pulse generation circuit 3 generates the Loran C signal, that is, the Loran C
It generates a pulse wave that is synchronized with the carrier wave, and based on the above-mentioned frequency-divided pulse,
A periodic pulse as shown in is generated at a repeating period like the Loran C pulse. Also, heliphase pulses b1, b7, bB,
b4 is generated at the same period of 10 usec as the Loran C carrier. And this synchronization pulse')i, b'2, b
3 and b4 are sent to the S/N detection pulse generation circuit 4, and at the same time, they are also sent to the switching circuit 5. The switching circuit 5 generates synchronizing pulses b1, b2, bB,
Switch and select one of the synchronization pulses from b4. On the other hand, the S/N detection pulse generation circuit 4 generates the synchronization pulse b
Eye detection pulses b1, b'h* bB1b4 corresponding to the respective synchronization pulses based on 1, bl, b111b4
Generate each. S/'N detection pulses C1, C9,
Each of C8 and C4 corresponds to a corresponding synchronization pulse b1.
, b7, bB, and b4 are generated with a delay of 2.5 usec. S/N detection pulse C1, C2, C8, C4
Each is a sampling circuit 7A.

75170, 7D separately. Each of the sampling circuits 7A, 7B, 70, -7D samples the Loran C signal (FIG. 2a) sent from the receiving amplifier 8. The respective sampling results are sent to each of the reversible counters 9A19B, 90, and 9D.

Each of the sampling circuits 7A17B170.7D sends out an addition pulse to the respective reversible counter when the sampling value of the Loran C signal is at a high level. Conversely, when the sampled value is at a low level, a subtraction pulse is sent to each reversible counter. Therefore, reversible counter 9A
, 9B, and 90.9D are bond detection pulses CI,
Each time C2, C8, and C4 samples the high level portion of the Loran C signal, an addition count is performed, and conversely, when the low level portion is sampled, a subtraction count is performed.

The respective count values of reversible counters 9A, 9B, and 90.9D are determined by discriminators 10A, IOB, 100,
Sent separately to each of the IODs. Discriminator 10A,
IOB, 100. Each of the IODs has a reversible counter 9
When each count value of A, 9B, and 90.9D is above a predetermined value, a high level output is sent out, and when the count value is smaller than a certain value 1, a low level output is sent out. In addition, discrimination 10A, IOB, 100.
The numerical value at which each IOD switches to a high level output and the numerical value l at which it switches to a low level output have a history system as described later.

Discriminator 10A, l0B1100. Each discrimination output of the IOD is sent to the logic circuit 6. The logic circuit 6 controls the switch circuit 5 based on the outputs of the discriminators 10A, 110B, 100, and IOD to generate synchronization pulses b1,
One of the synchronization pulses b7, bB, and b4 is selected by switching.

That is, discriminator 10A, IOB, 100110D
Synchronous pulses b1, b2, bB according to each output state of
, b4 is selected, and each discriminator 10
A, IOB, 100. The correspondence between the output state of the IOD and the selected synchronization pulses b0, b9, bB, and b4 is determined as shown in the table below. In the table below, H indicates a high level, L indicates a low level, and × indicates an indefinite level.

Among the synchronous pulses b1, b2, b8, and b4, the synchronous pulse selected as described above by the logic circuit 6 is selected by the switching circuit 5.
The signal is then sent to the phase comparator 11. The phase comparator 11 compares the phase of the synchronization pulse sent from the switching circuit 5 and the Loran C signal sent from the reception amplifier 8, and establishes phase synchronization between the synchronization pulse and the Loran C signal based on the comparison result. The phase of the synchronizing pulse is controlled so that the This phase control is performed by controlling the frequency dividing operation of the frequency dividing circuit 2 to advance or delay the phase of the synchronizing pulse.

Phase synchronization between the periodic pulse and the Loran C signal in the phase comparator circuit 11 is performed with respect to a specific phase of the Loran C signal. Generally, as is well known, phase synchronization is performed at three cycle positions (28 points of waveform a in FIG. 2) of the Loran C signal. In the embodiment shown in FIG. 1, it is assumed that the synchronizing pulse b1 is synchronized in phase with about 3 cycles %t (ps point) of the Loran C signal.

This phase synchronization is performed by observing the Loran C signal on a cathode ray tube, etc., when starting up the Loran 0 receiver, and then using the synchronization pulse b.
This is done by shifting the phase of 1 to 3 cycle position P8. Therefore, immediately after starting up the Loran C receiver, the output of the logic circuit 6 is forcibly set so that the switching circuit 5 sends out the synchronizing pulse b1. Immediately after the Loran C receiver is activated, the control circuit 12 forcibly sets the output state of the logic circuit 6 as described above.

The phase comparator circuit 11 has a synchronizing pulse bX of 3 of the Loran C signal.
After the phase is shifted to the cycle position P8, the phase of the synchronizing pulse b1 and the Loran C signal is compared, and the frequency dividing operation of the frequency dividing circuit 2 is controlled as described above based on the comparison result. After the phase comparison circuit 11 starts this phase control operation, the logic circuit $6 performs discriminators 10A, IOB, 100.
Based on the output of the IOD, the switching circuit 5 is caused to perform the switching operation as shown in Table 1 above. Although it is possible to automatically match the phase between the synchronous Hals b1 and the 3rd cycle position P8 of the Loran C signal, the present invention is capable of automatically matching the phase of the synchronous pulse b1 with the 3rd cycle position P8 of the Loran C signal. Since the purpose is to track the phase after synchronization, a description thereof will be omitted.

Synchronous pulse b is at 3-cycle position P8 of Loran C signal
When the phase is synchronized with the point, the sampling circuit 7A samples 97 points at high level positions 2.5 sec after the 3 cycle position P of the Loran C signal using the low detection pulse C1. The sampling circuit 7A sends out an addition pulse to the reversible counter 9A when the bond detection pulse C samples the high level position Q.

Discriminator 1. The OA sends out a high level output while the added value of the reversible counter 9A is above a certain value, and based on this, the logic circuit 6 causes the switching circuit 5 to send out a synchronizing pulse b1. As a result, synchronization pulse B, 3 of Nyororan C signal
Phase synchronization of cycle position P8 is maintained. If the S/N ratio of the Loran 0 signal is poor and the phase synchronization becomes unstable, the sampling result in the sampling circuit changes unstablely between high and low levels. The reversible counter 9A performs subtraction counting when the sampling result is at a low level, and when the subtraction value exceeds a certain value, the output of the discriminator 10A changes from a high level to a low level. here,
Discriminator 1 for reversible counter 9A. The level change of OA is set to have hysteresis characteristics.

That is, when the count value of the reversible counter 9A changes like a curve as shown in FIG. 3, when the count value is 1 (or more), the discriminator 10A sends out a high level output.
When the count value exceeds k and changes by 1 inch, the output of the discriminator 10A changes from a high level to a low level. Thereafter, the low level is maintained until the count value exceeds 1 and reaches k, and when the count value reaches k, the output of the discriminator 10A changes to high level again.

When the output of the discriminator 10A changes to a low level, the logic circuit 6 causes the switching circuit 5 to perform a switching operation according to Table 1. That is, when the output of the discriminator 10A is at a low level and the output of the discriminator 10B is at a high level, the synchronizing pulse b2 is sent out. Also, discriminator 1. When OB has a low level output, when the discriminator 100 has a high level output, it sends out a synchronizing pulse b8, and when the discriminator 1.00 also has a low level output, it sends out a synchronizing pulse by the high level output of the discriminator 10D. b4 is sent.

Discriminator 1 song, 100, IOD has respective reversible counters 9B, 90, 9D, sampling circuits 7B, 70
．． 7D, the seven sampling circuits, the reversible counter 9A, and the discriminator 10A operate in the same manner. Therefore, 3
When the phase synchronization at a cycle of 5 jPa is unstable,
When the sampling result obtained by the detection pulse C2 is stable at a high level, phase synchronization is performed by the synchronization pulse 1) at the fourth cycle position P4.

Furthermore, when the phase synchronization at the 4-cycle position P4 is unstable, the synchronization pulse bB or l)4 is similarly applied.
Phase synchronization is performed by Then, when the sampling result by the S/N detection pulse C1 stably remains at a high level again, the synchronization pulse 1].

Phase synchronization is performed again.

Synchronous pulses l) 1, b9, b8, b4 as above
While phase synchronization is performed between either of the two signals and the Loran C signal, the synchronization pulse b1 is sent to the time difference measuring circuit 14. The time difference measurement circuit 14 receives the synchronization pulse b and the synchronization pulse for the Loran C signal of another station, and measures the time difference between the synchronization pulses, but its operation will be omitted.

As described above, according to the present invention, when the phase synchronization at the 3rd cycle position of the Loran C signal is unstable, the phase synchronization is performed at the 4th cycle position or the 5th cycle position. And the time difference measurement is 3
Since this is done using a synchronization pulse that should be synchronized to the cycle position, the same effect as when synchronizing the Loran C signal and the synchronizing pulse is always performed at the 3rd cycle position of the Four Ran C signal can be obtained. Therefore, even when the reception state of the Loran C signal is relatively unstable, phase synchronization between the Loran C signal and the synchronization pulse can be performed. However, in the case of Loran C signal, 4 cycles, 5 cycles or 6 cycles
The cycle position may be affected by spatial waves. Accordingly, the indicator 13 indicates, based on the output of the logic circuit 6, if phase synchronization is not performed at the 3 cycle position. In addition, the synchronization pulse, S detection and re-response may be performed at least two times, in which case one of the tracking points and one of the tracking points may be used.
It is sufficient to compare S before the cycle. Sampling, determining devices, etc. can be miniaturized using a microgrossetzer. Furthermore, in FIG. 1, the switching circuit 5 is controlled by the logic circuit 6, but the switching operation of the switching circuit 5 is performed by reversible counters 9A, 9B, 90,
It may be performed manually according to the count value indicated by the count value of 9D.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram illustrating its operation, and FIG. 3 is a waveform diagram illustrating the operation of the discriminator. Applicant Furuno Electric Co., Ltd. No. 2. 4 -415- 3rd eye

Claims (1)

[Claims] A receiver for a Loran C signal; a first comparison pulse generation circuit that compares the received Loran C signal with a predetermined specific phase; A second comparison pulse generating circuit that is sent out after a certain time delay, an S-detector that detects the 8/N ratio of the received Loran 0 signal, and switching between the first and second comparison pulses. A switching circuit to select, and a phase comparison between the first and second comparison pulses sent from the switching circuit and the Loran C signal, and based on the comparison result, the comparison pulse is changed to the Loran C signal. It is characterized by comprising a synchronizing circuit that synchronizes with a predetermined phase position b' of the signal, and the switching operation of the switching circuit is performed in accordance with the ratio detected by the S/N ratio detector. Automatic tracking device for Loran C signal.