JPS5821569A - Battery checker circuit - Google Patents

Battery checker circuit

Info

Publication number
JPS5821569A
JPS5821569A JP12100381A JP12100381A JPS5821569A JP S5821569 A JPS5821569 A JP S5821569A JP 12100381 A JP12100381 A JP 12100381A JP 12100381 A JP12100381 A JP 12100381A JP S5821569 A JPS5821569 A JP S5821569A
Authority
JP
Japan
Prior art keywords
transistor
collector
emitter
voltage
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12100381A
Other languages
Japanese (ja)
Other versions
JPH0237548B2 (en
Inventor
Toshihide Miyake
敏英 三宅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP12100381A priority Critical patent/JPH0237548B2/en
Publication of JPS5821569A publication Critical patent/JPS5821569A/en
Publication of JPH0237548B2 publication Critical patent/JPH0237548B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G01R19/16542Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies for batteries

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To enable the detection of voltage in a wide range from a low power source voltage to about several volts by comparing collector current of transistors which are different in the emitter area while commonly connected in the base. CONSTITUTION:After a power source voltage to be detected is divided with a resistance R0, a voltage is applied in common to the bases of transistors (Tr) Q1 and Q2. The resistance R1 connected to the emitter of the TrQ1, the resistance R2 connected to the emitters of Trs Q1 and Q2 and the ratio of the emitter areas of the Trs are so designed that collector currents of the TrQ1 and TrQ2 coincide with each other at the state of the threshold voltage to be detected. Then, as the power source voltage rises, the collector current of the TrQ2 won't readily change because of the resistance R2 where as the collector current of the TrQ1 increases in a larger measure. This turns off the TrQ5 and turns on the TrQ7 which leads to a higher level of the output. On the contrary, when the power source voltage lowers, the TrQ5 is turned on and the TrQ7 turned off which leads to a lower level of the output.

Description

【発明の詳細な説明】 本発明は電圧レベルを検出するためのバッテリーチェッ
カー回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a battery checker circuit for detecting voltage levels.

電池駆動する電子機器では、電源電圧の低下に基因する
誤動作を防ぐために、通常電源電圧を検知するためのバ
ッテリーチェッカー回路が組み込まれている。しかし従
来から用いられているこの種の回路では、低い電源電圧
を検知させることが難しく、また検知のために設定し得
る電圧範囲も非常に狭いために適用範囲が限られたもの
にならざるを得なかった。
Battery-powered electronic devices usually include a battery checker circuit for detecting power supply voltage in order to prevent malfunctions due to a drop in power supply voltage. However, with this type of circuit that has been used in the past, it is difficult to detect low power supply voltages, and the voltage range that can be set for detection is very narrow, so the range of application is limited. I didn't get it.

本発明は上記従来回路の欠点に鑑みてなされたもので、
低い電源電圧、例えば1.5Vを下回る電圧から数V程
度まで広い範囲の電圧を検知電圧として設定し得るバッ
テリーチェッカー回路を提供するものである。
The present invention has been made in view of the drawbacks of the above-mentioned conventional circuits.
The present invention provides a battery checker circuit that can set a low power supply voltage, for example, a voltage in a wide range from less than 1.5V to several volts as a detection voltage.

次に図面を用いて本発明の詳細な説明する。Next, the present invention will be explained in detail using the drawings.

本発明はいわゆるパッドギャップ型の電圧検出回路とし
て構成され、要約すれば、検知すべき電源電圧を抵抗R
Qに印加して分圧を導出する。この導出された電圧を共
通に第1トランジスタQle第2トランジスタQ2のベ
ースに印加する。一方第1トランジスタQlのエミッタ
に抵抗R1を接続するのに対して、第1トランジスタQ
1のエミッタと第2トランジスタQ2のエミッタ間にも
抵抗R2を接続する。上記各抵抗及びトランジスタのエ
ミッタ面積の比及び抵抗R1,R2は検知すべきしきい
電圧の状態で第1トランジスタQ、と第2トランジスタ
Q2のコレクタ電流がほぼ一致す、るように設計される
。このように構成された回路において第1トランジスタ
Q1のコレクタ電流と第2ド2ンジスタQ2のコレクタ
電流を比較する比較回路を設けてその出力をバッテリー
チェッカー回路の出力とするものである。
The present invention is configured as a so-called pad gap type voltage detection circuit, and in summary, the power supply voltage to be detected is detected by a resistor R.
Apply it to Q to derive the partial pressure. This derived voltage is commonly applied to the bases of the first transistor Qle and the second transistor Q2. On the other hand, while a resistor R1 is connected to the emitter of the first transistor Ql,
A resistor R2 is also connected between the emitter of the first transistor Q2 and the emitter of the second transistor Q2. The ratio of the emitter areas of each of the resistors and transistors and the resistors R1 and R2 are designed so that the collector currents of the first transistor Q and the second transistor Q2 almost match each other in the state of the threshold voltage to be detected. In the circuit configured as described above, a comparison circuit is provided to compare the collector current of the first transistor Q1 and the collector current of the second transistor Q2, and the output thereof is used as the output of the battery checker circuit.

図において、検知すべき電源電圧vceと接地GND間
に抵抗RQが接続され、該抵抗RQの途中段によって分
割された電源VCCの分圧が導出され、’NPNからな
る第1トランジスタQl、第2トランジスタQ2更に第
6トランジスタQ6のベースに共通に印加される。ここ
で上記第1トランジスタQl と第2トランジスタQ2
は後述するように、検知すべき電源電圧のレベルでほぼ
コレクタ電流が一致するように回路が設計されるもので
、従ってまず所望のベース・エミッタ間電圧の差ΔVB
Eが得られるように両トランジスタのエミッタの面積が
互いに相異する形状に設計されている。
In the figure, a resistor RQ is connected between the power supply voltage vce to be detected and the ground GND, and the divided voltage of the power supply VCC divided by the intermediate stage of the resistor RQ is derived, and the first transistor Ql, which is made of NPN, and the second transistor It is commonly applied to the bases of the transistor Q2 and the sixth transistor Q6. Here, the first transistor Ql and the second transistor Q2
As will be described later, the circuit is designed so that the collector current almost matches the level of the power supply voltage to be detected. Therefore, first, the desired base-emitter voltage difference ΔVB
In order to obtain E, the emitter areas of both transistors are designed to have different shapes.

例えば夫々のトランジスタのエミッタ面積をEQI。For example, EQI the emitter area of each transistor.

EQ2とするとEol : E(12= 1 : I 
Oに設計される。
Assuming EQ2, Eol: E(12= 1: I
Designed to O.

第1トランジスタQ1Φエミツタには接地GNDとの間
に抵抗R1(IOKΩ)が接続され、第2トランジスタ
Q2のエミッタは抵抗R2(2にΩ)を介して上記第1
トランジスタQ1のエミッタに接続されている。両トラ
ンジスタQ1.Q2には更に両トランジスタのコレクタ
電流を比較して出力を導出するための回路が付加されて
いる0即ち、第1トランジスタQ1のコレクタ電流を第
2トランジスタQ2のコレクタに方向を変えて加え合せ
るために、PNP )ランジスタからなる第8トランジ
スタQ8及び第4トランジスタQ4で構成されたカレン
トミラー接続されている。該第8及び第4トランジスタ
Q8*Q4の共通接続されたベースは第1トランジスタ
Q、のコレクタに接続されている。第4トランジスタQ
4のコレクタに接続された上記第2トランジスタQ2の
コレクタはPNP第5トランジスタQ5のベースに接続
され、該第5トランジスタQ5のコレクタは第1.第2
トランジスタQIsQ2 とベースを共有する前記NP
N第6トランジスタQ6のコレクタに接続され、該第6
トランジスタQ6を能動負荷とする。第6トランジスタ
Q6のエミッタと接地GND間には上記抵抗R1と#1
は同じ抵抗値をもった抵抗R3(IOKΩ)が挿入され
ている。トランジスタ。I*Q2のコレクタ電流の比較
結果は、第5トランジスタ。5と第6トランジスタQ6
の両コレクタの接続点にベースが接続され、電源VCC
と接地GND間に抵抗R4(100KΩ)を介して接続
されたPNP第7トランジスタQ7のコレクタ端子OU
Tから導出される)次に上記構成からなる回路の動作を
説明する。
A resistor R1 (IOKΩ) is connected between the emitter of the first transistor Q1Φ and the ground GND, and an emitter of the second transistor Q2 is connected to the emitter of the first transistor Q1 through a resistor R2 (Ω to 2).
Connected to the emitter of transistor Q1. Both transistors Q1. Q2 is further provided with a circuit for comparing the collector currents of both transistors and deriving an output. In other words, in order to add the collector current of the first transistor Q1 to the collector of the second transistor Q2 by changing the direction. , an eighth transistor Q8 consisting of a PNP transistor, and a fourth transistor Q4, which are connected in a current mirror manner. The commonly connected bases of the eighth and fourth transistors Q8*Q4 are connected to the collector of the first transistor Q. 4th transistor Q
The collector of the second transistor Q2 connected to the collector of the first transistor Q2 is connected to the base of a PNP fifth transistor Q5, and the collector of the fifth transistor Q5 is connected to the collector of the first transistor Q5. Second
The NP sharing a base with the transistor QIsQ2
connected to the collector of the Nth sixth transistor Q6;
Transistor Q6 is used as an active load. The resistor R1 and #1 are connected between the emitter of the sixth transistor Q6 and the ground GND.
A resistor R3 (IOKΩ) having the same resistance value is inserted. transistor. The comparison result of the collector current of I*Q2 is the fifth transistor. 5 and the sixth transistor Q6
The base is connected to the connection point of both collectors, and the power supply VCC
The collector terminal OU of the seventh PNP transistor Q7 is connected through a resistor R4 (100KΩ) between the
(derived from T) Next, the operation of the circuit having the above configuration will be explained.

まず電源電圧が検知すべきしきい電圧の状態での動作を
説明する。
First, the operation when the power supply voltage is the threshold voltage to be detected will be explained.

今、第1トランジスタ。1と第2トランジスタQ2はエ
ミッタ面積がIi:Ql : EQ2= I : I 
OK設ジスタQ2のVBEとの差ΔvaBは、vBE=
KT/q@1nIc/Ioの式よシΔvBE=KT/q
111n1゜となる。上記ΔVBHの値は20℃程度の
雰囲気で動作させた場合、約60mVになる。即ち、2
にΩに設計された上記抵抗R2の両端に60mVの電圧
が印加されるような電流が流れたとき、第1トランジス
タQ1と第2トランジスタQ2のコレクタ電流の値は一
致する。この状態で抵抗R1には第1トランジスタQl
からの電流に加えて第2トランジスタQ2からの電流が
流れ込むため2倍の電流が流れる。また抵抗R1の値は
抵抗R2に対してR1=5Rgに設計されてい゛るため
、抵抗R1には600mVの電圧が生じる。一方第1ト
ランジスタQlには30μAのコレクタ電流が流れてい
るため、第1トランジスタQ1のペース・エミッタ間電
圧VBHには20℃の雰囲気で、通常の集積回路を構成
、するトランジスタのβ=100程度の条件を適用する
ことにより約650mVとなる。このような動作状棟を
導く第1トランジスタQ+、第2トランジスタQ2のペ
ース電位を求めると、1.25Vとなる。
Now the first transistor. 1 and the second transistor Q2 have an emitter area of Ii:Ql:EQ2=I:I
The difference ΔvaB between OK setting resistor Q2 and VBE is vBE=
The formula of KT/q@1nIc/Io is ΔvBE=KT/q
111n1°. The value of ΔVBH is about 60 mV when operated in an atmosphere of about 20°C. That is, 2
When a current flows such that a voltage of 60 mV is applied across the resistor R2, which is designed to have a resistance of Ω, the values of the collector currents of the first transistor Q1 and the second transistor Q2 match. In this state, the resistor R1 is connected to the first transistor Ql.
In addition to the current from the second transistor Q2, the current from the second transistor Q2 flows, so twice as much current flows. Further, since the value of the resistor R1 is designed to be R1=5Rg with respect to the resistor R2, a voltage of 600 mV is generated at the resistor R1. On the other hand, since a collector current of 30 μA flows through the first transistor Ql, the pace-emitter voltage VBH of the first transistor Q1 is approximately β = 100 of a transistor that constitutes a normal integrated circuit in an atmosphere of 20°C. By applying the following conditions, it becomes approximately 650 mV. The pace potential of the first transistor Q+ and the second transistor Q2 that lead to such a behavior pattern is 1.25V.

即ち、抵抗RQによって分圧され電圧が1.25Vの状
轢で両トランジスタQItQ2のコレクタ電流が等しく
なり、電源電圧が設定値レベルであることを示す。尚抵
抗RQの分圧点を移動させることによって検知すべき電
源電圧vccのレベルを変えることができる。
That is, when the voltage is 1.25V divided by the resistor RQ, the collector currents of both transistors QItQ2 become equal, indicating that the power supply voltage is at the set value level. Note that by moving the voltage dividing point of the resistor RQ, the level of the power supply voltage vcc to be detected can be changed.

次に上記ペース電位の温度特性を考える。両トランレス
タのベース−エミッタ間電圧の差ΔVBEは絶対温度に
比例する特性をもつことから、20℃の動作温度に対し
て+(、’/263 )/℃の温度特性を示し、600
mVに対しては+2.04mシrとなる。
Next, consider the temperature characteristics of the pace potential. Since the difference ΔVBE between the base and emitter voltages of both transistors has a characteristic that is proportional to the absolute temperature, it exhibits a temperature characteristic of +(,'/263)/℃ for an operating temperature of 20℃, which is 600℃.
For mV, it is +2.04m sir.

一方集積化されたトランジスタのペース・エミッタ間電
圧VBEはKT/q−InIC/Io で表わされて、
完全な直線とはいえないが、コレクタ電流Ic=30μ
八程度では−2,05m’/cとなり、上記ベース・エ
ミッタ間電圧の差ΔVBHの温度特性(+2.04mV
/C)とほぼ打ち消し合い、結局はとんど温度特性を持
たなくなる。即ち、上記第1トランジスタQ1と第2ト
ランジスタQ2のコレクタ電流を比上記動作は第1トラ
ンジスタQ1 と第2トランジスタQ2が一致する状態
で説明したが、両トランジスタQ1.Q2のベース電位
が上った場合を説明する。第2トランジスタQ2のコレ
クタ電流はエミッタ端子に接続された抵抗R2のために
容易に変化せず、第1トランジスタQ、のコレクタ電流
の増加の方が大きく、このとき第5トランジスタQ5は
オフし、第7トランジスタQ7はオシになって、第7ト
ランジスタQ7のコレクタ端子から導出された出力は高
レベル即ち(Wee−0,1V程度)となって高電位で
あることを示す。逆にベース電位が下った場合は、第5
トランジスタQ5がオンし、第7トランジスタQ7がオ
フして出力レベルは低レベルとなって、電源電圧に対応
した抵抗RQの分圧で電圧レベルを検知して出力信号を
形成する。検知すべき電源電圧は上記両市力信号の境界
で検知される。
On the other hand, the pace-emitter voltage VBE of an integrated transistor is expressed as KT/q-InIC/Io,
Although it is not a perfect straight line, the collector current Ic = 30μ
At around 8, it becomes -2.05 m'/c, and the temperature characteristic of the base-emitter voltage difference ΔVBH (+2.04 mV
/C), and in the end almost no temperature characteristics are found. That is, the collector currents of the first transistor Q1 and the second transistor Q2 are compared. Although the above operation has been explained with the first transistor Q1 and the second transistor Q2 being the same, the collector currents of the first transistor Q1 and the second transistor Q2 are the same. A case where the base potential of Q2 rises will be explained. The collector current of the second transistor Q2 does not change easily because of the resistor R2 connected to the emitter terminal, and the increase in the collector current of the first transistor Q is greater, and at this time the fifth transistor Q5 is turned off. The seventh transistor Q7 is turned on, and the output derived from the collector terminal of the seventh transistor Q7 is at a high level, that is, about (Wee-0.1V), indicating a high potential. Conversely, if the base potential drops, the fifth
The transistor Q5 is turned on, the seventh transistor Q7 is turned off, and the output level becomes a low level, and the voltage level is detected by the voltage division of the resistor RQ corresponding to the power supply voltage to form an output signal. The power supply voltage to be detected is detected at the boundary between the two power signals.

処でバッテリーチェッカー回路で問題となるのは、判定
点より電源電圧レベルが更に下った場合に、出力が反転
して誤まった出力信号を導出することを防がねばならな
い。しかし上記実施例に示した回路では前記のような誤
動作の惧れは全くない。即ち第」トランジスタQ1と第
2トランジスタQ2のコレクタ電流を比較するための回
路は、第3トランジスタQ8と第4トランジスタQ4か
らなるカレントミラーを利用して第1トランジスタQl
の電流の向きを変えて加え合せる構成をとっている。こ
こでPNP )ランジスタはβが小さいため第1トラン
ジスタQ1のコレクタ電流と第4トランジスタQ4のコ
レクタ電流が等しくならないという問題があるが、これ
を打ち消すために第6トランジスタQ5のベース電流を
第3.第4トラ゛/ジメタQ3.Q4のベース電流の和
に等しくしてバランスさせている0但し第8及び第4ト
ランジスタQ3.Q4のコレクタ電流は第1トランジス
タQl又は第2トランジスタQ2のコレクタ電流から第
3.第4トランジスタQ8.Q4のペース電流を減じた
ものであるのに対して、第5トランジスタQ5のコレク
タ電流は第6トランジスタQ6のコレクタ電流から第7
トランジスタQ7のペース電流を減じたもので、第6ト
ランジスタQ6のコレクタ電流は第1.第2コレクタ電
流Ql 、Q2のコレクタ電流の和に等しくできる。従
って集積回路内に作られるラテラルPNP )ランジス
タのような低いβのトランジスタでカレントミラーを構
成した場合でも、カレントミラー利得に起因する電流比
較の誤差を第5トランジスタQ5のベース電流で打ち消
すことができ、精度の向上を図ることができ、また設定
電圧に応じて抵抗R4の値を変えることによって完全な
バランス状態を得ること可能で、より特性の安定したチ
ェック回路が得られる。
However, the problem with the battery checker circuit is that it must be prevented from inverting the output and deriving an erroneous output signal when the power supply voltage level drops further below the decision point. However, in the circuit shown in the above embodiment, there is no risk of malfunction as described above. That is, the circuit for comparing the collector currents of the first transistor Q1 and the second transistor Q2 uses a current mirror consisting of the third transistor Q8 and the fourth transistor Q4 to compare the collector currents of the first transistor Q1 and the second transistor Q2.
The structure is such that the directions of the currents are changed and added together. Here, the PNP transistor has a problem in that the collector current of the first transistor Q1 and the collector current of the fourth transistor Q4 are not equal because β is small, but in order to cancel this, the base current of the sixth transistor Q5 is changed to the third transistor. 4th TRAVEL/JIMETA Q3. Q4 is balanced by equalizing the sum of the base currents of the eighth and fourth transistors Q3. The collector current of Q4 is varied from the collector current of the first transistor Ql or the second transistor Q2 to the collector current of the third transistor Q1. Fourth transistor Q8. The collector current of the fifth transistor Q5 is the collector current of the sixth transistor Q6 minus the pace current of the seventh transistor Q4.
The collector current of the sixth transistor Q6 is the same as that of the first transistor Q6. The second collector current Ql can be made equal to the sum of the collector currents of Q2. Therefore, even if the current mirror is configured with low β transistors such as lateral PNP transistors created within the integrated circuit, the error in current comparison caused by the current mirror gain can be canceled out by the base current of the fifth transistor Q5. , accuracy can be improved, and a perfectly balanced state can be obtained by changing the value of the resistor R4 according to the set voltage, resulting in a check circuit with more stable characteristics.

以上本発明によれば、分圧を引き出す抵抗値を変えるこ
とによって広い範囲の電源電圧を検知することができ、
特に低い電圧を検知電圧とすることができ電池駆動用機
器に最適のバッテリーチェッカー回路となる0また温度
特性がすぐれ検知動作にバラツキがない等実用価値の高
いバッテリーチェック回路が得られる。
As described above, according to the present invention, a wide range of power supply voltages can be detected by changing the resistance value that draws out the partial voltage.
In particular, it is possible to use a low voltage as the detection voltage, making it an optimal battery checker circuit for battery-powered equipment.In addition, a battery check circuit with high practical value such as excellent temperature characteristics and no variation in detection operation can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明による一実施例の電気回路図である。 Q+ 、Q2 、Qs : NPN )’ランジスタ、
Q3,04g5.Q7  : PNP トランジスタ、
RQ 、R1、R2。 R9,R4:抵抗0 代理人 弁理士 福 士 愛 彦
The figure is an electrical circuit diagram of an embodiment according to the present invention. Q+, Q2, Qs: NPN)' transistor,
Q3,04g5. Q7: PNP transistor,
RQ, R1, R2. R9, R4: Resistance 0 Agent Patent attorney Aihiko Fukushi

Claims (2)

【特許請求の範囲】[Claims] (1)  エミッタ面積が互いに異なり、且つベースが
共通に接続された第1トランジスタQ1及び第2トラン
ジスタQ2と、エミッタ面積の小さい第1トランジスタ
Qlのエミッタと接地間に挿入された抵抗R1と、上記
両トランジスタQl。 Q2のエミッタ間に接続された抵抗R2と、電源vCC
と接地間に接続され且つ上記トランジスタQl、Q2の
共通接続されたベースに分圧した電圧を与えるだめの抵
抗RQと、上記両トランジスタQ1#Q2のコレクタ電
流を比較して出力を導出する比較回路とを備えてなるバ
ッテリーチェッカー回路。
(1) A first transistor Q1 and a second transistor Q2 whose emitter areas are different from each other and whose bases are connected in common; a resistor R1 inserted between the emitter of the first transistor Ql whose emitter area is small and the ground; Both transistors Ql. Resistor R2 connected between the emitter of Q2 and the power supply vCC
a resistor RQ connected between and ground and for applying a divided voltage to the commonly connected bases of the transistors Ql and Q2, and a comparator circuit that compares the collector currents of both the transistors Q1 and Q2 and derives an output. A battery checker circuit equipped with
(2)前記比較回路は、第1トランジスタQlのコレク
タ電流を第2トランジスタQ2のコレクタに与えるだめ
の第3及び第4トランジスタQa。 Q4からなるカレントミラーと、第2トランジスタQ2
のコレクタにベースが接続された第5ト多ンジスタQ5
と、該第5トランジスタQ5のコレクタにコレクタが接
続され且つベースが第1.第2トランジスタQ、、Q2
のベースと共通に接続された第6トランジスタQ6と、
該第6トランジスタQ6のエミッタと接地間に接続され
た上記抵抗R1とほぼ同じ抵抗値を持つ抵抗゛R8とを
含んでなることを特徴とする特許請求の範囲第(1)項
記載のバッテリーチェッカー回路0
(2) The comparison circuit includes third and fourth transistors Qa that supply the collector current of the first transistor Ql to the collector of the second transistor Q2. A current mirror consisting of Q4 and a second transistor Q2
A fifth transistor Q5 whose base is connected to the collector of
, the collector is connected to the collector of the fifth transistor Q5, and the base is connected to the collector of the first transistor Q5. Second transistor Q,,Q2
a sixth transistor Q6 commonly connected to the base of
The battery checker according to claim 1, further comprising a resistor R8 connected between the emitter of the sixth transistor Q6 and the ground and having substantially the same resistance value as the resistor R1. circuit 0
JP12100381A 1981-07-31 1981-07-31 BATSUTERIICHETSUKAAKAIRO Expired - Lifetime JPH0237548B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12100381A JPH0237548B2 (en) 1981-07-31 1981-07-31 BATSUTERIICHETSUKAAKAIRO

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12100381A JPH0237548B2 (en) 1981-07-31 1981-07-31 BATSUTERIICHETSUKAAKAIRO

Publications (2)

Publication Number Publication Date
JPS5821569A true JPS5821569A (en) 1983-02-08
JPH0237548B2 JPH0237548B2 (en) 1990-08-24

Family

ID=14800370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12100381A Expired - Lifetime JPH0237548B2 (en) 1981-07-31 1981-07-31 BATSUTERIICHETSUKAAKAIRO

Country Status (1)

Country Link
JP (1) JPH0237548B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59176680A (en) * 1983-03-26 1984-10-06 Toshiba Corp Current detecting circuit
JPS62162973A (en) * 1986-01-13 1987-07-18 Oki Electric Ind Co Ltd Power sensing circuit
FR2640095A1 (en) * 1988-08-22 1990-06-08 Nat Semiconductor Corp INTEGRATED LOCKING CIRCUIT AT LOW SUPPLY VOLTAGES

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59176680A (en) * 1983-03-26 1984-10-06 Toshiba Corp Current detecting circuit
JPS62162973A (en) * 1986-01-13 1987-07-18 Oki Electric Ind Co Ltd Power sensing circuit
FR2640095A1 (en) * 1988-08-22 1990-06-08 Nat Semiconductor Corp INTEGRATED LOCKING CIRCUIT AT LOW SUPPLY VOLTAGES

Also Published As

Publication number Publication date
JPH0237548B2 (en) 1990-08-24

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