JPS58215105A - Amplifying circuit - Google Patents

Amplifying circuit

Info

Publication number
JPS58215105A
JPS58215105A JP57097926A JP9792682A JPS58215105A JP S58215105 A JPS58215105 A JP S58215105A JP 57097926 A JP57097926 A JP 57097926A JP 9792682 A JP9792682 A JP 9792682A JP S58215105 A JPS58215105 A JP S58215105A
Authority
JP
Japan
Prior art keywords
resistor
power supply
constituting
differential amplifier
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57097926A
Other languages
Japanese (ja)
Inventor
Hidemi Ueno
秀己 上野
Shigeru Nakajima
茂 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57097926A priority Critical patent/JPS58215105A/en
Publication of JPS58215105A publication Critical patent/JPS58215105A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To decrease a time remarkably from the application of power supply to the normal operating state, so-called leading time, by applying a bias voltage a half the power supply voltage to bases of both transistors (TR) constituting a differential amplifier via a resistor respectively, for forming a capacitor constituting a feedback circuit so as to be charged quickly via a resistor at the application of power supply. CONSTITUTION:A voltage a half a power supply voltage Vcc obtained from a voltage source is impressed to a capacitor C4 immediately via a resistor R6. Thus, a base unit of the other TRQ5 constituting a differential amplifier is brought into a half the power supply voltage Vcc quickly and the entire amplifying circuit is brought into the normal operating state very quickly in comparison with the case without the resistor R6. For example, in using several kilohms of the resistor R6, the time becoming the normal operating state is about several hundreds msec, allowing to reduce the time to about 1/10 in comparison with the case without the resistor R6.

Description

【発明の詳細な説明】 本発明はテープレコーダ等の各種音響機器に使用する低
周波増幅回路に係り、簡単な構成で素早< iE常な動
作状態に立上る優れた増幅回路を提供することを目的と
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low frequency amplification circuit used in various types of audio equipment such as tape recorders, and an object of the present invention is to provide an excellent amplification circuit that has a simple configuration and quickly rises to a normal operating state. This is the purpose.

一般にテープレコーダに使用する増幅回路は録音釦や再
生釦を押圧操作し、これによって電源をオンすると直ち
に正常な動作状態になるものが要求される。従来より1
吏用されているこの種の増幅回路は電源投入時の■上り
が必ずしも素早くなく録音、再生時にはそれぞれ最初の
部分が途切れてしまうという問題点があった。
Generally, an amplifier circuit used in a tape recorder is required to be in a normal operating state as soon as the record button or play button is pressed and the power is turned on. 1 more than before
This type of amplifier circuit currently in use had the problem that it did not always go up quickly when the power was turned on, and the first portions of both recording and playback would be interrupted.

本発明は以上のような従来の欠点を除去するものであり
、電源投入から正常な動作状態になるまでのいわゆる立
上り時間を著しく短かくできる優ねた増幅回路を提供す
るものである。
The present invention eliminates the above-mentioned conventional drawbacks and provides an excellent amplifier circuit that can significantly shorten the so-called rise time from power-on to normal operation.

以下、本発明の増幅回路について一実施例の図面ととも
に説明する。図において、D1〜D4.R1R2,Ql
、Q2はそわぞれ電源電圧vcc の−の電圧を得るだ
めの亀用源を構成するダイオード、抵抗、トランジスタ
でありダイオードD1.抵抗R1゜ダイオ〜ドD2.D
3.抵抗R2,ダイオードD4はそれぞれ互に直列に接
続され抵抗R1とダイオードD2との接続点、ダイオー
ドD3と抵抗R2の接続点がそれぞれ互に直列に接続さ
れた上記トランジスタQ1.Q2のベースに接続されて
いる。Q4.Q6はぞれぞれエミッタが互に接続さiま
た差動増幅器を構成するトランジスタであり、一方のト
ランジスタQ4のベースは抵抗R3を介して上記電圧源
を構成するトランジスタQ1.Q2のエミッタに接続さ
れ、同時に結合コンデンサC1を介して信号入力端子a
に接続されている。C3,<−はそれぞれカレントミラ
ー回路を構成するトランジスタ。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The amplifier circuit of the present invention will be described below with reference to drawings of an embodiment. In the figure, D1 to D4. R1R2, Ql
, Q2 are diodes, resistors, and transistors that constitute a power source for obtaining the negative voltage of the power supply voltage vcc, respectively, and the diodes D1 . Resistor R1゜Diode D2. D
3. The resistor R2 and the diode D4 are connected in series with each other, and the transistor Q1. Connected to the base of Q2. Q4. Q6 are transistors whose emitters are connected to each other and constitute a differential amplifier, and the base of one transistor Q4 is connected via a resistor R3 to the transistors Q1 . connected to the emitter of Q2, and at the same time via the coupling capacitor C1 to the signal input terminal a.
It is connected to the. C3 and <- are transistors forming a current mirror circuit, respectively.

ダイオードであり、上記差動増幅器の能動負荷として作
用するようにそれぞれ上記差動増幅器を構成するトラン
ジスタQ4.Q5のコレクタに接続されている。C7は
ベースが上記差動増幅器を構成。
transistors Q4 . Connected to the collector of Q5. The base of C7 constitutes the above differential amplifier.

する一方のトランジスタQ4のコレクタに接続された出
力用のトランジスタであり、その出力端すなわちコレク
タは結合コンデンサC3を介して出力端子すに接続され
ている。C6,C8はそれぞれベースが電圧源を構成す
る抵抗R2とダイオードD4の接続点に接続された定電
流源用のトランジスタであり、上記一方のトランジスタ
Q6のコレクタは差動増幅器を構成するトランジスタQ
4.Q6の共通エミッタに、上記他方のトランジスタQ
8のコレクタは−に記出力用トランジスタQ7のコレク
タにそれぞれ接続されている。尚、C2は出力用トラン
ジスタQ7のコレクタと差動増幅器を構成する一方のト
ランジスタQ4のコレクタとの間に接続された位相補償
用のコンデンサ、R4,R6C4は交流及び直流帰還回
路を構成する抵抗、コンデンサ、R6は電圧源を構成す
るトランジスタQ1.Q2のエミッタと差動増幅器を構
成する他方のトランジスタQ5のベースとの間に接続さ
れた抵抗、C5は電源端子■ccとアースとの間に接続
されたコンデンサ、SWは電源スィッチである。
This is an output transistor connected to the collector of one transistor Q4, and its output terminal, that is, the collector, is connected to the output terminal S via a coupling capacitor C3. C6 and C8 are constant current source transistors whose bases are connected to the connection point of the resistor R2 and the diode D4, which constitute a voltage source, and the collector of one of the transistors Q6 is connected to the transistor Q which constitutes a differential amplifier.
4. The other transistor Q is connected to the common emitter of Q6.
The collectors of the transistors 8 and 8 are respectively connected to the collectors of the output transistors Q7. Note that C2 is a phase compensation capacitor connected between the collector of the output transistor Q7 and the collector of one transistor Q4 forming the differential amplifier, R4 and R6C4 are resistors forming the AC and DC feedback circuits, The capacitor R6 is a transistor Q1. which constitutes a voltage source. A resistor is connected between the emitter of Q2 and the base of the other transistor Q5 constituting the differential amplifier, C5 is a capacitor connected between the power supply terminal cc and ground, and SW is a power switch.

上記実施列において、今、抵抗R6がないものとする。In the above implementation row, it is assumed that there is no resistor R6.

この状態において電源スィッチSwをオンしたとすると
次のような経過を経て増幅回路全体が正常な動作状態に
なる。すなわち、電源スィッチSWをオンすると先ず、
ダイオードD1〜D4゜抵抗R1,R2,トランジスタ
Q1.Q2より成る電圧源に所定の電流が流れる。した
がって、電圧源を構成するトランジス、JQ4.C2の
接続点には電源スィッチSWのオンと同時に電源電圧v
ccの一のMugが現われる。そして、ここに現われだ
電圧tよ抵抗R3を介して差動増幅器を構成する一方の
トランジスタQ4のベースに印加される。差動増幅器を
構成する他方のトランジスタQ6のベースは帰還回路を
構成する抵抗R5,コンデンサC4を介してアースされ
ており、この状態では未だコンデンサC4が充電されて
いないだめほぼアース毘 電位にある。しだがって差動増幅器を構成する一方のト
ランジスタQ4はほぼ完全にオンの状態になり、出力ト
ランジスタQ7もほぼ完全にオンの状態になる。したが
って、この状態では入力端子aより信号が印加されたと
してもほとんど増幅作用がなく、増幅回路としての機能
を果たさない。
If the power switch Sw is turned on in this state, the entire amplifier circuit enters a normal operating state through the following process. That is, when you turn on the power switch SW, first,
Diodes D1 to D4, resistors R1, R2, transistor Q1. A predetermined current flows through the voltage source made up of Q2. Therefore, the transistors forming the voltage source, JQ4. At the connection point of C2, the power supply voltage V is applied at the same time as the power switch SW is turned on.
A Mug from cc appears. The voltage t appearing here is applied via the resistor R3 to the base of one transistor Q4 constituting the differential amplifier. The base of the other transistor Q6 constituting the differential amplifier is grounded via a resistor R5 and a capacitor C4 constituting a feedback circuit, and in this state is almost at ground potential unless the capacitor C4 is charged yet. Therefore, one transistor Q4 constituting the differential amplifier is almost completely turned on, and the output transistor Q7 is also almost completely turned on. Therefore, in this state, even if a signal is applied from the input terminal a, there is almost no amplification effect, and the circuit does not function as an amplifier circuit.

い状態にある。したがってコンデンサC4は抵抗R4,
R5を介してこの電圧により充電が開始されることにな
る。コンデンサC4への充電が進行し位と同じように電
源電圧V。Cの2になると差動増幅器が正常な動作状態
になり、出力用トランジスタQ7も同様に正常な動作状
態になる。すなわち抵抗R6がない場合には差動増幅器
を構成する他方のトランジスタQ5のベース電位が電源
電圧vcoの百になるまでに少なくとも抵抗R4,R6
゜コンデンサC4によって決定される一定時間必要とな
り、それだけ増幅回路が正常な動作状態になるのが遅れ
ることになる。
It is in a bad condition. Therefore, capacitor C4 is resistor R4,
Charging will be started by this voltage via R5. The power supply voltage V increases as the charging of capacitor C4 progresses. When C becomes 2, the differential amplifier enters a normal operating state, and the output transistor Q7 similarly enters a normal operating state. In other words, if there is no resistor R6, at least the resistors R4 and R6 are removed before the base potential of the other transistor Q5 constituting the differential amplifier reaches 100% of the power supply voltage vco.
A certain period of time determined by the capacitor C4 is required, which delays the amplifier circuit from reaching its normal operating state.

具体的には増幅回路全体の利得を考慮して抵抗R4が数
1oKΩ、抵抗R5が数10〜数1000コンデンサC
4が数1007zFに選ばれることが多いため、増幅回
路が正常な動作状態になるまでに数秒を必要とすること
になる。
Specifically, considering the gain of the entire amplifier circuit, the resistor R4 is several tens of kilohms, and the resistor R5 is several tens to several thousand ohms of capacitor C.
4 is often selected to be several 1007 zF, so it takes several seconds for the amplifier circuit to become in a normal operating state.

ところが上記実施列によれば抵抗R6が挿入されている
ため、電圧源で得られた電源電圧vcc。
However, according to the above embodiment, since the resistor R6 is inserted, the power supply voltage vcc obtained from the voltage source.

1の電圧が抵抗R6を介して直゛ちにコンデンサC4に
印加されることになり、差動増幅器を構成する他方のト
ランジスタQ6のベース単位を素早く電源電圧vccの
iにすることができ、抵抗R6がない場合に比して著し
く早く増幅回路全体を正常な動作状態にすることができ
る。たとえば抵抗R6としてdKΩのものを用いると正
常な動作状態になるまでの時間を約a100m秒にする
ことができ抵抗R6がない場合に比して約10分の1に
することができる。
1 voltage is immediately applied to the capacitor C4 via the resistor R6, and the base unit of the other transistor Q6 constituting the differential amplifier can be quickly set to i of the power supply voltage vcc. The entire amplifier circuit can be put into a normal operating state much faster than when R6 is not provided. For example, if a dKΩ resistor is used as the resistor R6, the time required to reach the normal operating state can be reduced to approximately a100 msec, which is approximately one tenth of the time required without the resistor R6.

なお、実施例において抵抗R1,R2,R6,R5の値
やコンデンサC4,C5の値は小さければ小さい方か正
常な動作状態になるまでの時間を短かくすることができ
る。そして抵抗R4,R6,R6の値は次の関係にある
ことが望ましい。
In addition, in the embodiment, the smaller the values of the resistors R1, R2, R6, and R5 and the values of the capacitors C4 and C5 are, the shorter the time until the normal operating state is achieved. It is desirable that the values of the resistors R4, R6, and R6 have the following relationship.

R5<R6くR4 以上、実施例により明らかなように、本発明の増幅回路
によれば簡単な構成で定常な動作状態になるまでの時間
を著しく短かくすることができ、実用l二きわめて有利
なものである。
R5<R6<R4 As is clear from the examples above, according to the amplifier circuit of the present invention, the time required to reach a steady operating state can be significantly shortened with a simple configuration, which is extremely advantageous in practical use. It is something.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の増幅回路における一実施例の電気的結線図
である。 瓢pダ 〜〜 0.ダイオード、Q1〜Q8・・・・・・トラン
ジスタ、R1−R6−・−抵抗、C1〜C6・・コンデ
ンサ、SW・・・・・電源スイッチ、a −入力端子、
b・・・・・・出力端子。
The figure is an electrical wiring diagram of one embodiment of the amplifier circuit of the present invention. Gourd pda~~ 0. Diode, Q1-Q8...Transistor, R1-R6--Resistor, C1-C6...Capacitor, SW...Power switch, a - Input terminal,
b...Output terminal.

Claims (1)

【特許請求の範囲】 差動増幅器を構成する一方のトランジスタのベースに入
力信号を印加し、他方のトランジスタのベースに上記差
動増幅器の後段に接続された出力トランジスタの出力の
一部を抵抗7コンデンサより成る帰還回路を介して帰還
するように構成すると共に上記差動増幅器を構成する両
トランジスタの1   + ベースにそれぞれ抵抗を介して電源電圧のiの・・イア
スミ圧を供給し、上記帰還回路を構成する上記コンデン
サを電源投入時に上記抵抗を介して素早く充電するよう
に構成した増幅回路。
[Claims] An input signal is applied to the base of one transistor constituting a differential amplifier, and a part of the output of an output transistor connected to the rear stage of the differential amplifier is connected to the base of the other transistor through a resistor 7. It is configured to feed back via a feedback circuit consisting of a capacitor, and an Iasmi pressure of i of the power supply voltage is supplied to the bases of both transistors constituting the differential amplifier through resistors, respectively, and the feedback circuit An amplifier circuit configured to quickly charge the capacitor constituting the circuit through the resistor when power is turned on.
JP57097926A 1982-06-07 1982-06-07 Amplifying circuit Pending JPS58215105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57097926A JPS58215105A (en) 1982-06-07 1982-06-07 Amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57097926A JPS58215105A (en) 1982-06-07 1982-06-07 Amplifying circuit

Publications (1)

Publication Number Publication Date
JPS58215105A true JPS58215105A (en) 1983-12-14

Family

ID=14205280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57097926A Pending JPS58215105A (en) 1982-06-07 1982-06-07 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS58215105A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4525367Y1 (en) * 1968-12-12 1970-10-05
JPS5531324A (en) * 1978-08-29 1980-03-05 Fujitsu Ltd Transient noise preventing circuit
JPS55163905A (en) * 1979-06-07 1980-12-20 Nec Corp Feedback amplifier
JPS5620312A (en) * 1979-07-27 1981-02-25 Pioneer Electronic Corp Reference voltage generating circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4525367Y1 (en) * 1968-12-12 1970-10-05
JPS5531324A (en) * 1978-08-29 1980-03-05 Fujitsu Ltd Transient noise preventing circuit
JPS55163905A (en) * 1979-06-07 1980-12-20 Nec Corp Feedback amplifier
JPS5620312A (en) * 1979-07-27 1981-02-25 Pioneer Electronic Corp Reference voltage generating circuit

Similar Documents

Publication Publication Date Title
JP3125282B2 (en) Audio signal amplifier circuit and portable audio device using the same
JPS5836015A (en) Electronic variable impedance device
US5815034A (en) Capacitive coupling circuit with diode-biased differential amplifier
JPS58215105A (en) Amplifying circuit
JPS6142887B2 (en)
KR100291237B1 (en) Clamp circuit
JP2698201B2 (en) Video head amplifier
KR100239602B1 (en) Voice signal recorder
JPS58103207A (en) Power supply circuit of amplifier
JPH0161247B2 (en)
JP3530326B2 (en) Amplifier
JPH0112417Y2 (en)
JPS5827537Y2 (en) Complementary push-pull amplifier
JPS648954B2 (en)
JP3208915B2 (en) Reproducing circuit for magnetic head
JP2557398B2 (en) Amplifier circuit
JP2538013Y2 (en) High pass filter circuit
JPH0716138B2 (en) Amplifier circuit device
JPH0345568B2 (en)
JPS61105917A (en) Low voltage buffer circuit
JPS609206A (en) Bias circuit
JP3041917B2 (en) Peak hold circuit
JPS6115619Y2 (en)
JPS58219806A (en) Amplifier circuit
JPH0336100Y2 (en)