JPS58214954A - Storing system of large capacity data - Google Patents

Abstract

PURPOSE:To realize the uniform staging, by estimating the access frequency of the near future from the present access frequency for each storage device to store it and then comparing the estimated access value with that generated actually to replace the next estimated access value. CONSTITUTION:Access frequency counters CTR1-CTRn within a counting part 20 count the access frequencies of sections of the present time and in correspondence to high-speed storage devices 1-n. Registers REG1-REGn of storage part 60 store the estimated values of present time section calculated at the end of the pre-time sections of the devices 1-n. A high-speed storage device number designating signal DNO is supplied to selectors 10, 40, 50 and 70 to switch them successively. For instance, n=1 is selected to read out the difference of contents between the counter CTR1 and the register REG1. Then the difference of contents is multiplied 95 by a constant ALPHA and then added 45 with the contents of the counter CTR1. Thus the contents of the REG1 are replaced. The signal DNO is successively switched from 1 to (n) to replace the contents of all high- speed storage devices. Thus a high-speed storage device of a low access frequency is selected before staging to ensure the unform access frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a hierarchical control mechanism for stored data in a large-capacity data storage system. The present invention relates to a mechanism for optimally selecting a specific high-speed storage device as a staging destination when staging data from a storage device to a high-speed storage device.

(2) Description of the Prior Art In the hierarchical control mechanism of conventional large-capacity data storage systems, when data is staged from a low-speed storage device to a high-speed storage device (for example, from a data cartridge containing a magnetic tape medium to a staging magnetic disk When staging data to a device), a simple method has been used to select a specific high-speed storage device as a staging destination without considering the access frequency of that device. As a result, during actual system operation, the frequency with which each high-speed storage device is accessed by the host operating system varies greatly. The drawback was that the above-mentioned bottleneck phenomenon often occurred.

(3) Detailed Description of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art, and therefore, an object of the present invention is to: By predicting the future access frequency of each high-speed storage device based on information about past access frequencies, it is possible to select a high-speed storage device with a low access frequency as a staging destination, thereby The object of the present invention is to provide a new large-capacity data storage system in which access frequencies between storage devices are statistically equalized and there is no performance bottleneck.

(4) Detailed Description of the Invention In order to achieve the above object, the large-capacity data storage system according to the present invention includes a counting means for counting the current access frequency of each high-speed storage device of the system, and a storage means for storing predicted information regarding the access frequency for each high-speed storage device; a means for reading out the contents stored in the storage means as needed; and a storage means for reading out the contents stored in the storage means based on the counting result of the counting means. We have a means to update it regularly.

Therefore, according to the present invention, the large-capacity data storage system can constantly predict the access frequency of each high-speed storage device in the system in the near future;
By staging as much as possible on high-speed storage devices that are expected to be accessed less frequently when a staging request is generated, it is possible to equalize the access frequency among the high-speed storage devices.

(5) Description of principle and operation of the invention In the present invention, a linear prediction filter as described below is used in order to predict the access frequency of each high-speed storage device in the near future. As shown in FIG. 1, it is assumed that the flow of time is divided into time intervals t1, t2.1, t1, t1, ti++, etc., each having a certain length. In each time interval, the access frequency of each high-speed storage device in that time interval is counted and the predicted information of the access frequency of each high-speed storage device in the next time interval is calculated. In practice, for the former, one counter is prepared for each high-speed storage device, and the values of all argument counters are cleared to "0#" at the beginning of the time interval.
Thereafter, the number of accesses to each high-speed storage device is counted until the end of that time interval. In this case, the high-speed storage device k (k = 1.2,...
, tL) is expressed as fk (t is expressed by Fk(t()), then for the latter, at the end of time interval 1<, the high-speed storage device k for the next time interval j4++
Fk ('Jet) is calculated as predicted information of the access frequency of Ck=1, R, . . . using the following equation.

Fh (tI++) =Fh (t() xα+fk(
t=) ...(1) k=12. ＊ ＊ ＊,
n However, α is a constant such that 0≦α<1, and k is the device number of the high-speed storage device. If we do this, then according to filter theory, the fast storage device k (
It is known that the total access frequency of &=x, a, . . . , n) can be predicted with high accuracy using the following equation.

fk (j(+s) −(1−α)XFk(ti+1
) ...(2) k-151, @ fist*, % The following equation can be easily obtained from the recurrence equation of equation (1) and equation (2).

? &(js++)=(1-α)[fk(jj)-1-α
4k(U-+)+α2・fk(t(-z)+α3・fk
(ti-s)+...]...(3) That is, (1)
, predicting the total access frequency of each high-speed storage device in the time interval 'j4++ using equation (2) means (
3) As is clear from the equation, the weighted average is calculated by applying a geometric weight to the actual measured value of the total access frequency in each past time interval for each high-speed storage device, such that the closer to the current time interval, the heavier the access frequency is. This corresponds to taking a certain amount of money. (1), (
The prediction method using a linear prediction filter according to equation 2) is understood to be a good method.

In the case of optimally selecting a high-speed storage device as a staging destination when an actual staging request occurs in a mass data storage system, the above technique can be used in the following manner. First, an explanation of this method at an arbitrary point in time is illustrated in FIG. 2. Figure 2 shows all the numerical information that needs to be maintained regarding the operating status of each high-speed storage device at that point, assuming that this arbitrary point is at a certain point during the time interval ti++. . That is, according to this method, at this arbitrary point in time, prediction information Fk (jj++) of the total access frequency expected during the time interval 'Jet and the time interval j (++) are calculated for each high-speed storage device. The total access frequency (fk*
Two types of information (expressed as (ji+t)) are maintained. Here, f&(t(++)= (1-α)
When calculating XFk(t(++), time interval t(+1
This is the predicted value for the value of fk*(j(++) (that is, fk (U++)) at the end of the process.

In this way, by maintaining the above two types of information for each high-speed storage device, it is possible to predict the access frequency of each high-speed storage device in the near future fairly accurately at all times. As a result, in a large-capacity data storage system, when an actual staging request occurs, the access frequency prediction information for each high-speed storage device is checked and the staging destination data area is allocated on the device with the lowest possible access frequency prediction information. This makes it possible to equalize the frequency of access to each high-speed storage device thereafter. In this way, the problem of the bottleneck of specific high-speed storage devices, which is one of the drawbacks of conventional large-capacity data storage systems, can be solved.

(6) Detailed Description of the Invention Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 3 is a block configuration diagram showing one embodiment of the present invention. One embodiment of the present invention includes a counting unit that counts the number of star accesses up to the current point in the current time interval of each high-speed storage device. , a storage unit 60 that stores predicted information on the total number of accesses in the current time interval to each high-speed storage device, and this storage unit 6
A reading unit 80 for reading out the memory contents of 0, and a storage unit 6
The update section 90 is configured to update the stored contents of 0 based on the counting result of the counting section 20 using the above equation (1).

The operation of the system according to the present invention will be described below with reference to FIG. 3, assuming that the system is now at the point where time interval t7 is about to begin. At this point, the number of accesses counting column 7 existing in the counting section, /CTRI
, CTR2, . Register JRE for predicting the number of accesses existing in the section 60
GI, BEG 2, ..., REGn C, which correspond to high-speed storage devices 1.2, ..., n, respectively) are each high-speed storage device for the current time period calculated at the end of the previous time period. (predicted total number of accesses).

Under these conditions, at the beginning of time interval 1, the host operating system begins accessing each high-speed storage device. Therefore, in the present invention, the number of the high-speed storage device to be accessed is first given as the DNO signal shown in FIG. 3. At this time, the selector 10
The DNO signal is transmitted to the selector 10, and the selector 10 generates and transmits the @1" signal only to the counter for counting the number of accesses corresponding to the high-speed storage device specified by the DNO signal. Here, the contents of the counter for counting the number of accesses are transmitted. When the count-up signal CNT for counting up by 1 is set to '1#, only the contents of the access count counter selected by the DNO signal are counted up by 1. In this way, each high-speed storage device is Accesses can be counted one by one.

On the other hand, when a staging request occurs in a mass data storage system as the host operating system runs, it becomes necessary to know the numbers of high-speed storage devices that are expected to be accessed less frequently from this point on. For this purpose, registers REGI and BEG for predicting the number of accesses are required.
2,---1iGn (7) It is necessary to read out the contents sequentially. In the present invention, first, the number of the high-speed storage device is given as a DNO signal. Then, this signal is transmitted to the selector 70, and the access count prediction register REG
I, BEG2, 1-1 REGn output 61.62.1-
16n that corresponds to the high-speed storage device specified by the DNO signal and outputs it as is as the output of the selector 70. Here, if the iAD signal is set to "1",
The output of selector 70 is read into data register DR. As a result, it becomes possible to read the information for predicting the total number of accesses of the high speed storage device specified by the DNO signal. By repeating the above operation for each high-speed storage device, the contents of all access count prediction registers can be read.

As described above, the total number of accesses to each high-speed storage device within time interval 1< This allows the total number of access prediction information to be read out.

Then, as time passes and the end of time interval t(, it becomes necessary to prepare for the next time interval t(+s.
The contents of GI, lG2, ---1REGn are converted to the above (
1) Updating according to the formula and the access count counting column y l CTRI , CTR2, ..., CTRn
It is necessary to clear the contents to '0#. To this end, in the present invention, the number of the high-speed storage device is first given as a DNO signal. This signal is transmitted to the selector 70, and the contents of the access count prediction register selected by this signal are transmitted to one input side of the multiplier 95 as the output of the selector 70. On the other hand, 75 (ALPHA) is a circuit that generates a constant α, and its output is transmitted to the other input side of the multiplier 95. Here, when the UDI signal is set to 1'', the multiplication result (that is, Fk(tt,) xα) is output, and this is transmitted as one input of the adder 45. DNO for input
The contents of the access count counter selected by the signal are transmitted as the output of the selector 40. therefore,
Here, when the UD2 signal is further set to "1#," the adder 45 outputs the addition result (i.e., Fk (j<)
b)) is transmitted to the selector 50.

This selector 50 is a selector for directly transmitting the output of the adder 45 to the access count prediction register corresponding to the designated number of the DNO signal. Therefore, in this case, the addition result (Fk(t)×α+fh
(t
(Access count prediction information for +1 (Fk (tj+
t) )).

By repeating the above operation corresponding to all high-speed storage devices by changing the value of the DNO signal, the contents of all the access count prediction registers are displayed in the next time period t(+1
Updates in preparation for this will be completely completed. Here, if the CLR signal is set to 1", the access count counters CTRI, CTR2°..., CTRn which are no longer necessary
The contents of are all cleared to 0''.

In this way, all preparations for the next time interval i(+t) are completed. Hereinafter, exactly the same operation as described above can be continued for the next time interval tt+t. Therefore, the above By way of illustration, one embodiment of the invention shown in FIG. 3 performs all of the above-described operations for purposes of the invention.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an example, and it goes without saying that the present invention is not limited only to the embodiment described herein.

(7) Detailed Description of the Invention As explained above, the present invention makes it possible to predict the access frequency of each high-speed storage device in a large-capacity data storage system, thereby making it possible to predict the access frequency of each high-speed storage device in a large-capacity data storage system. In selecting a specific high-speed storage device, it is possible to select a high-speed storage device with a low access frequency, thereby eliminating performance bottlenecks in system operation as a result of statistical equalization of access frequencies among each high-speed storage device. This can have the effect of avoiding the occurrence of.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the access frequency prediction method applying filter theory, which is the basis of the present invention, and Figure 2 is an illustration of Jin's access frequency prediction method applied to a large-capacity data storage system based on the present invention. FIG. 3, which is an explanatory diagram of conceptual operation, is a block configuration diagram showing an embodiment of the present invention. 1.2,...,n...high speed storage device, 10
．． 40.50.70...Selector, 11.12,
..., In...... Output of selector 10, addition...
. . . Counting units 21, 22, which count the cumulative number of accesses of each high-speed storage device up to the present time in the current time interval;
..., 2n... Output of counter for counting the number of accesses, 45... Adder, 51.52,...
..., 5n... Output of selector 50, 60...
. . . Storage unit 61, 62, .
・, 6n: Output of the access count prediction register, 75 (ALPHA): Constant generation circuit,
80... A portion for reading out the storage contents of the storage section 60, 90... An updating section for updating the storage contents of the storage section 60 based on the counting result of the counting section, 95
...Multiplier, DNO...High-speed storage device number designation signal, CLR...Clear request signal, C
NT...Count up request signal, READ/
...read request signal, UDl...first update request signal, UD2...second update request signal,
UD3...Third update request signal, CTRL, CT
R2, @@Ill, CTRn-- Counter for counting the number of accesses, REGl, REG2, ... REGn...
...Register for predicting the number of accesses, DR...
・Data Register Patent Applicant NEC Co., Ltd. Agent Patent Attorney Yutabe Kumagai Takashi Kojiya ・1.Breath wick pre-soaking 1m・1Upper 100% off Figure 2

Claims (1)

[Claims] a counting means for counting the current access frequency for each storage device; a storage means for storing predicted information on the access frequency for each storage device in the near future; a means for reading out the contents stored in the storage means; A large-capacity data storage system comprising means for updating stored contents based on the counting result of the counting means.