RU2099783C1 - Device for on-line control of aircraft which belongs to groups - Google Patents

Abstract

FIELD: data processing equipment for optimal control of aircraft groups under different effects against ground aircraft control center. SUBSTANCE: device provides possibility to use automatic choice which is based on stochastic programming which choice criteria are maximal mean usefulness of control method, maximal probability that usefulness will reach pre- set threshold β. EFFECT: increased reliability, increased speed of decision making for selection of optimal control method, increased functional capabilities due to possibility to solve stochastic programming tasks. 1 dwg , 1 tbl

Description

 The present invention relates to devices for data processing and can be used to prepare and develop the optimal solution for choosing the method of controlling the groupings of aircraft (LA) with various factors affecting the ground control complex of the aircraft.

 At present, to work out a decision on choosing the optimal aircraft control method, by which we mean the system of rules that determine the functioning of the aircraft ACS, we use groups of specialists who algorithmically or heuristically solve this problem in flight control centers. As public analogues of the invention, it is proposed to use ed. St. N1295412, 1305705, 1309034.

 However, further complication of the aircraft, the composition of the aircraft groupings now leads to an increase in the number of specialists solving this problem, and the costs of providing the management process increase. Along with this, the time for processing the incoming volumes of information and choosing the optimal control method increases, which is unacceptable in difficult operating conditions. It should be borne in mind that with a direct impact on the management process, the reasonableness of management decisions will fall based on the psychological properties of a person, as well as the possible absence of qualified specialists.

 The closest in technical essence is a device for optimizing the distribution of resources with saturable needs (see ed. St. N1298763, CL G 06 F 15/20, 1987), containing counters, memory blocks, comparison blocks, decoders, registers, elements delays, blocks of elements OR. The device provides a solution to the problem of linear programming. The basis of the invention is a simple finite iterative algorithm that allows you to use the features of the problem, expressed in the simple structure of the constraint system.

 However, this device does not allow the use of various criteria and selection indicators that are optimal for specific operating conditions in a stochastic (probabilistic) description of the situation.

 The technical task of the invention is to increase the reliability and speed of decision-making on choosing the optimal control method, expanding the functionality of the device by solving stochastic programming problems.

 The solution to the technical problem is achieved by providing the possibility of using an automated selection mechanism based on the stochastic programming method with selection criteria (A): maximizing the mathematical expectation of the "utility" of the control method (1), maximizing the probability of exceeding the "utility" of the control method of the given threshold β (2).

где i порядковый номер метода управления,

М количество методов управления;
j порядковый номер фактора воздействия,

N количество факторов воздействия (см. Б.А.Резников. Теория систем и оптимального управления. Ч. 3. Принятие решения в условиях неопределенности и адаптации. МО СССР, 1988, с.45 47).

where i is the serial number of the control method,

M is the number of management methods;
j is the sequence number of the exposure factor,

N is the number of impact factors (see B. A. Reznikov. Theory of systems and optimal control. Part 3. Decision-making under conditions of uncertainty and adaptation. Ministry of Defense of the USSR, 1988, p. 45 47).

As an indicator of choice, i.e. The “usefulness” of the control method for various impact factors characterized by the probability of occurrence of these factors ω _j will take the specific effectiveness of using the control method for a given exposure. The specific effectiveness of the method is characterized by the probability of fulfilling the target task of the aircraft (R _cz ) depending on the cost of the costs of the functioning of the ACS (C) means determined by this control method.

В зависимости от условий функционирования можно варьировать удельным весом Р_цз и С в "полезности" метода. Мирное время отдаем предпочтение стоимости, военное время вероятности выполнения целевой задачи ЛА.

Depending on the operating conditions, it is possible to vary the specific gravity P _cz and C in the "utility" of the method. Peacetime preference is given to cost, wartime is the probability of the fulfillment of the aircraft’s target.

The drawing shows a diagram of the proposed device operational control of aircraft included in the group, where
1 control unit;
2 clock generator;
3 first counter (Sch1);
4 first switch (Km1);
5 first memory unit (BP1);
6 second memory unit (BP2);
7 third memory block (BP3);
8 first block of OR elements;
9 first register (Pg1);
10 second register (Pg2);
11 third register (Pg3);
12 first delay element (Ez1);
13 second switch (Km2);
14 block of registers (1.N);
15 decoder;
16 first comparison unit (Cp1);
17 second delay element (Ez2);
18 second block of OR elements;
19 first block of key elements (Cl1);
20 second block of key elements (Cl2);
21 multiplication blocks;
22 third block of OR elements;
23 second counter (Sch2);
24 adder;
25 third element of delay (Ez3);
26 fourth register (Pg4);
27 fourth element of delay (Ez4);
28 second comparison unit (Esr2);
29 third block of key elements (Cl3);
30 fifth register (Pg5).

 The output of the clock generator 2 is connected to the read inputs of the first 9 and second 10 registers connected by the outputs to the first inputs of the first 4 and second 13 switches, and to the input of the first counter 3, connected by the output to the second input of the first switch 4 and through the first delay element 12 s the input of the decoder 15, the outputs of the first switch 4 are connected to the inputs of the first 5, second 6 and third 7 memory blocks, the outputs of which are connected through the first block of elements OR 8 to the second input of the second switch 13, the first output of which is connected with the first input of the first comparison unit 16, connected by the second input to the output of the third register 11, and the second output of the second switch 13 is connected to the first input of the second block of key elements 20 and through the second delay element 17 with the first input of the multiplication unit 21, the second input of which is connected to the output of the second block of key elements 20 connected by the second input to the output of the second block of OR elements 18 and to the first input of the first block of key elements 19, the output of the multiplication unit 21 is connected to the first input of the third block of OR elements 22, the second input of which is connected to the output of the first block of key elements 19, the first input of which is connected to the output of the first block of comparison 16, the outputs of the decoder 15 are connected respectively to the read inputs of the block of registers 14, the outputs of which are connected to the inputs of the second block of elements OR 18, the first output of the decoder 15 connected to the zeroing inputs of the second counter 23, the adder 24 connected by the information input to the output of the third block of OR elements 22, and the fourth register 26, the last output of the decoder 15 is connected to the counting input the second counter 23, to the read input of the adder 24, the output connected to the first input of the second comparison unit 28 and through the third delay element 25 with the information input of the fourth register 26, and to the read input of the fourth register 26, the recording input of which is connected to the output of the second comparison unit 28 and to the first input of the third block of key elements 29, the second input of which through the fourth delay element 27 is connected to the output of the second counter 23, the output of the third block of key elements 29 is connected to the input of the fifth register 30, outputs b control windows 1 are connected respectively to the information inputs and recording inputs of the first 9, second 10, third 11 registers and block of registers 14, the start input of the clock 2, connected by the stop input to the output of the last bit of the first counter 3, and to the input of resetting the first counter 1 , the read input of the third register 11 is connected to the output of the second register 10.

 A priori device operates as follows.

 A priori, memory blocks 5, 6, 7 record the "utility" of control methods for various factors affecting the aircraft's ground-based control complex (the number of rows of memory blocks is equal to the number of methods, the number of columns to the number of types of influences). The “usefulness” of the first memory block 5 is equal to the management efficiency without taking into account the costs of its maintenance, the second memory block 6 is the cost of the costs without considering the efficiency, the third memory block 7 is the specific control efficiency of the aircraft. "Utility" is determined during preliminary modeling of aircraft control processes. Writing information to blocks 5, 6, 7 is not considered, since it is not involved in the operation of the device.

 Using the control unit 1, the operator writes to the register block 14 the probabilities of the occurrence of impact factors (in peacetime, these may be the probabilities of various states of the ground-based control complex that affect the control performance of the aircraft: difficult operating conditions of the ACS, interference, large load of ACS elements, etc. d.). The number of N registers is determined by the number of exposure factors. The threshold value β is recorded in the register 11; the excess by the “utility” of which is guaranteed with maximum probability. In register 9, the number of the "utility" option is written (blocks 5 or 6 or 7), in register 10, the option of choosing the control method of the aircraft (first or second) is written.

 From control unit 1, the operator resets the counter 3 with a signal and starts the clock generator 2, the pulses from which are sent to counter 3, forming the address of the "utility" element, as well as to the read input of register 9, the contents of which serve as a control signal for switch 4, which provides the opening of one of the memory blocks 5, 6, 7. The output signal from the GTI 2 also arrives at the read input of the register 10, the contents of which is a control signal for the switch 13 and a read signal of the register 11. At the input of the switch 13 Without block 8, the "utility" signals of one of the memory blocks are received in order. If the control signal opens the first output of the switch 13, then the pulses from the block of elements 8 are fed to the second input BSr1 16, the first input of which receives the value of register 11. If b is less than the signal from the output Km2 13, then the output 16 generates a pulse that allows passage through the key Кl1 19 the values of the block of registers 14 through the elements of block 18. The registers of block 14 are read by signals from the decoder 15, the input of which through the delay element 12 receives signals from the output of counter 3. If the control signal from register 10 opens the second output switch 13, then the value from the memory unit enters through the delay element 17 to the second input of the multiplier 21 and the input of the block 20, allowing the passage of signals from one of the registers of the block 14 to the first input of the multiplier 21. The second block of key elements 20 serves to synchronize the receipt of codes on the multiplication block 21, providing the input to its input of the code from block 18 only while simultaneously passing to another input of the code from element 17. Block 20 generates an output pulse to enable the passage of the signal from element 18 upon receipt of any and h of the values of memory blocks 5, 6, 7. Signals from the output of blocks 19 and 21 through block 22 are fed to the input of the accumulating adder 24, to the other input of which there is a pulse to resolve the sum from the last output of the decoder 15, when a signal proportional to the value comes to its input N + 1, where N is the number of registers in block 14. Counter 23 counts the number of pulses to enable the issuance of the sum, which is also the address of the control method. The address of the control method through the delay element 27 will be input to Кl3 29 and, according to the enable signal from Bsr2 28, will be written to register 30. Counter 23 and register 26 are reset to zero by the pulse from the first output of decoder 15. The operation of counter 3, decoder 15 and counter 23 is described in the table 1, in which the output values of these elements are shown in steps. For example, the option with N = 3, M = 2 is considered (the decoder has 5 outputs).

Если А>0, то А будет записываться в регистр 26 через элемент задержки 25 по сигналу записи из блока сравнения 28, который также является разрешающим сигналом прохождения адреса метода управления из блока 27 для блока 29. Второй сигнал с последнего выхода дешифратора обеспечивает сравнение В и А по второму методу управления (при i=2

) и при А>В значение А будет записываться в регистр 26 как и в предыдущем случае. Таким образом, в регистре 26 после каждой итерации остается максимальное значение суммы А. Устройство завершает свою работу, когда на выходе счетчика 3 будет сформирован адрес, превышающий количество значений используемого блока памяти. Этот адресный сигнал остановит ГТИ 2. В результате в регистре 30 останется адрес оптимального метода управления.The enable pulse of the issuance of the amount from the decoder 15 also reads the register 26, which is intended for intermediate storage of the maximum value of the sum of codes (A), which is generated in the block 24 in the interactive mode for each control method. The operation of block 26 is as follows. First, the signal from the first output of the decoder 15 register 26 is reset. According to the first signal from the last output of the decoder, the contents of block 26 (B) are supplied to the first input of the comparison unit 28, the second input of which receives the value of the sum A of block 24, which was obtained after the first iteration (i = 1,

If A> 0, then A will be written to register 26 through the delay element 25 according to the write signal from the comparison unit 28, which is also an enable signal for passing the control method address from block 27 for block 29. The second signal from the last output of the decoder compares B and And according to the second control method (for i = 2

) and when A> B, the value of A will be written to register 26 as in the previous case. Thus, in register 26, after each iteration, the maximum value of sum A remains. The device completes its work when an address exceeding the number of values of the used memory block is generated at the output of counter 3. This address signal will stop the GTI 2. As a result, the address of the optimal control method will remain in register 30.

The device uses elements that are widely used in aircraft control:
as a control unit 1, a code generation and transmission device can be used (see I.E. Soloveichik. Displays in computer systems. M. Sovetskoe Radio, 1979, UDC 681.327.23, p. 79 79, Fig. 11.50);
as blocks 8, 18, 22, a set of OR elements is used in the form of a line of logical elements at 3, N and 2 inputs, respectively, which ensure the transfer of a parallel code;
as blocks of key elements 19, 20 can be considered a set of logical elements And;
counters with feedbacks can be used as counters 3, 23 (see Fundamentals of discrete ACS and communication technology. Edited by G.F. Grinenko. L. MO USSR, 1980, UDC 658.5.012.011.56: 621.391 (075.8), p.334 -338, fig. 9.12);
as an adder 24, an accumulative type adder can be used (see Fundamentals of the design of electronic computers and computer systems. M: Statistics, 1975, UDC 6F7.3 (07) 075, p. 113, Fig. 5.11).

Claims (1)

 The operational control device for aircraft included in the groupings, containing the first and second counters, three memory blocks, two comparison units, a decoder, the first fifth registers, the first fourth delay elements, the first block of OR elements, characterized in that a register block is inserted into it, an adder, two switches, the second and third blocks of OR elements, three blocks of key elements, a multiplication unit, a control unit and a clock generator, the output of which is connected to the read input of the first and second registers, with connected to the outputs of the first inputs of the first and second switches, and to the input of the first counter connected by the output to the second input of the first switch and through the first delay element with the input of the decoder, the outputs of the first switch are connected to the inputs of the first, second and third memory blocks, the outputs of which are connected through the first block of OR elements to the second input of the second switch, the first output of which is connected to the first input of the first comparison unit connected by the second input to the output of the third register, and the second output is second of the first switch is connected to the first input of the second block of key elements and through the second delay element to the first input of the multiplication block, the second input of which is connected to the output of the second block of key elements connected by the second input to the output of the second block of OR elements and to the first input of the first block of key elements, the output of the multiplication block is connected to the first input of the third block of OR elements, the second input of which is connected to the output of the first block of key elements, the first input of which is connected to the output of the first block Ia, the outputs of the decoder are connected respectively to the readout inputs of the register block, the outputs of which are connected to the inputs of the second block of OR elements, the first output of the decoder is connected to the zeroing inputs of the second counter, adder connected to the information input with the output of the third block of OR elements, and the fourth register, the last output the decoder is connected to the counting input of the second counter, to the reading input of the adder, the output connected to the first input of the second comparison unit and through the third delay element with information ion input of the fourth register, and to the reading input of the fourth register, the recording input of which is connected to the output of the second comparison unit and to the first input of the third block of key elements, the second input of which through the fourth delay element is connected to the output of the second counter, the output of the third block of key elements is connected to the input of the fifth register, the outputs of the control unit are connected respectively to the information inputs and recording inputs of the first, second, third registers and block of registers, the start input of the clock generator pulses connected to the stop input with the output of the last discharge of the first counter, and to the input of zeroing the first counter, the read input of the third register is connected to the output of the second register.

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