JPS58213347A - Microprocessor - Google Patents

Abstract

PURPOSE:To execute each instruction code freely, by constituting a microinstruction storage section of a fixed memory and a variable memory, and rewriting the content of the variable memory by an instruction code from an external circuit. CONSTITUTION:A micro mu instruction storage section 40 consists of the fixed memory 90 and the variable memory 80, in a mu processor having an instruction register 10, a mapping memory 20, a sequencer 30, a micro mu instruction storage section 40, a pipeline register 50, a sequencer control section 60 and an operation control section 70. The memory 90 is resident with a write mu instruction generating a control signal to rewrite the mu instruction. An instruction code from an external instruction code is added with a control bit a data bus 11 and this instruction code is added with a control bit representing whether or not the code is the rewrite instruction of the mu instruction. The memory 80 checks this control bit and when the code is the rewrite instruction code of the mu instruction, the content of the memory 80 is changed according to a prescribed form. Thus, each instruction code is executed freely according to each individual instruction code.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor, and more specifically, to a microprocessor having a function of rewriting the contents of a microinstruction storage section for generating control signals. As shown in FIG. 1, the microprocessor has an instruction register 10 and a mapping memory 20.
, a sequencer 30, a microinstruction storage unit 40, a pipeline register 50, a sequencer control unit 60,
It is established from the arithmetic control section 70.

In FIG. 1, an instruction code is read into an instruction register 10 from an external instruction storage section via a data bus 11.

The instruction code read into the instruction register 10 is input to the sequencer 30 via the mapping memory 20, and the sequencer 30 generates a microinstruction address.The microinstruction address is transferred to the microinstruction address bus 31.
The output of the microinstruction storage unit 40 is inputted to the pipeline register 50 via the data output lot 41. The contents of the pipeline register 50 are transferred to the control bus 51 to the sequencer control unit ω.
added via . On the other hand, the contents of the pipeline register (equipment) are also added to the arithmetic control section 7o, and the instruction code is executed in the arithmetic control section 70.

In the conventional microprocessor shown in FIG. 1, the microinstruction storage unit 40 is constituted by a read-only memory (ROM), so the control signals generated by the instruction codes are one-to-one with the instruction codes. Please take care of υ,
The control signal is uniquely determined. therefore,
A disadvantage is that instruction codes used in one type of microprocessor cannot be used in another type of microprocessor.

Therefore, if you want to run existing microprocessor software on another microprocessor, you must use software modified from the source program. Therefore, the drawback is that a great deal of effort must be put into nine programs.

An object of the present invention is to configure a microinstruction storage unit with a fixed memory and a variable memory, rewrite the contents of the variable memory with an instruction code read from an external instruction storage unit,
It is an object of the present invention to provide a microprocessor which is equipped with a function to execute each instruction code according to each individual Hatake command code.

A microprocessor according to the invention has an instruction register;
It consists of a mapping memory, a sequencer, a micro-instruction storage section, a pipeline register, a sequencer control section, and an arithmetic control section, and the micro-instruction storage section consists of a fixed memory and a 7-variable memory. In this microprocessor, an external instruction code can rewrite the contents of the variable memory using instruction codes read from the microprocessor.

Hereinafter, details of the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing a portion of an embodiment of a microprocessor according to the present invention.

In FIG. 1, the microinstruction storage unit 80 is a variable memory 80.
The variable memory 80 is formed from the fixed memory (1) and the fixed memory (1).
It is connected to an external instruction storage unit via a data bus 11, and the microinstructions stored in the variable memory IJ80 can be rewritten via the data bus 11.

Fixed memory 90 permanently stores rewriting microinstructions for generating control signals for rewriting microinstructions.

The fixed memory 90 is composed of a read-only memory (ROM) and has a relatively small capacity.

The external instruction storage unit stores developed or newly developed software in the form of instruction codes.
Further, each instruction code has a control pit added thereto to indicate whether or not it is a microinstruction rewriting instruction.

According to the microprocessor according to the present invention, the control bits added by the variable memory 80 in FIG. 2 are checked, and it is determined whether or not it is a microinstruction rewriting instruction code.

If it is a microinstruction rewriting instruction code, the contents of the variable memo 1J80 are changed according to a predetermined format.

As an embodiment of the software pond in the present invention, the microinstruction code is defined in advance, and
There is also a method in which a microinstruction corresponding to this instruction code is made to reside inside a fixed memory. In this case, checking whether it is a microinstruction rewriting instruction code is done by knowing the state set in a state flip-flop provided in variable memory, and this flip-flop can be accessed by the output command of a normal program. By doing so, the instruction code system can be easily switched.

As explained above, in the microprocessor according to the present invention, it is possible to specify the microinstruction code generated in response to a specific instruction code. This is not necessary, and the advantage is that instructions and codes can be executed by the microprocessor according to the invention.

In addition, in software development, designers have a large degree of freedom in language selection, and microinstruction rewriting instructions can be freely mixed with normal instruction codes, which improves the efficiency of subroutines used and increases the number of program steps. It also has the effect of being able to shorten the time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional microprocessor, and FIG. 2 is a block diagram showing an embodiment of a microprocessor according to the present invention, which is an improved version of the microprocessor shown in FIG. 10... Instruction register 11.31.41.51.52... Bus 20... Mapping memory 30... Sequencer 40... Micro instruction storage unit 50... Pipeline register 60... Sequencer control section 70...Arithmetic control section 80...Variable memory 90 inside the microinstruction storage section...Fixed memory inside the microinstruction storage section

Claims (1)

[Claims] instruction register, mapping memory, sequencer,
The microprocessor includes a microinstruction storage unit, a pipeline register, a sequencer control unit, and an arithmetic control unit, and the microinstruction storage unit includes a fixed memory and a variable memory, and an external instruction storage unit A microprocessor comprising a function of rewriting the contents of the variable memory using an instruction code read from the microprocessor.