JPS58212379A - Reproducing speed controller - Google Patents

Abstract

PURPOSE:To smoothly control a motor from stationary to the rated rotation by applying a fixed voltage to an object to be controlled for the prescribed period at the starting time, then discriminating the reproducing speed by a discriminator and switching it to a normal speed control. CONSTITUTION:A signal produced by a pickup 3 from a recording medium 2 such as a disc or the like is applied to a synchronizing signal detector 4 and a reproducing speed detector 5, switched by a switching circuit 6, thereby controlling a motor 1 through a frequency voltage converter 8 and a drive circuit 15. A fixed voltage 20 is provided, and connected to a converter 22 which converts it with a signal of a discriminator 21 which discriminates whether the pickup 3 produces a signal or not. Accordingly, the voltage 20 is applied to rotate the motor 1 in the state that the disc 2 is stopped, and switched to the normal speed control when the signal can be produced by the pickup 3, thereby preventing the abnormal operation at the starting time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a motor playback speed control device for smoothly bringing the signal playback speed of a signal playback device for digitally recorded disks, tapes, etc. to a target speed.

When recording digital information on a recording medium such as a disk or tape, a synchronization signal is generally added, and during reproduction, this synchronization signal is detected and the reproduction speed is controlled so that the period of this synchronization signal is constant. As an example of this, Figure 1 shows the PCM
A block diagram of a playback speed control circuit of a disc playback device is shown.

In FIG. 1, 1 is a motor, 2 is a disk, and 3 is a big-up C or lower PU. ), 4 is a synchronization signal detection circuit that detects a synchronization signal from among the signals picked up by PU3,
5 is another reproduction speed detection circuit. Here, the playback speed detection circuit 5 detects that the playback speed of the device is determined by the synchronization signal detection circuit 4.
This is used when the signal exceeds the detection range of This is a speed detection circuit that predicts the synchronization signal period by multiplying the pulse width by eight. 6 is a switching circuit, 7 is a switching control circuit, 8 is a frequency-voltage conversion circuit (hereinafter referred to as f-V converter), and constant current source 16
゜Delay circuit 9. Pulse generation circuits 10, 11. Integral capacity 12. It consists of switches 14 and 17 and a hold capacitor 13. 15 is the drive circuit of motor 1, 19
is a gain digital processing circuit for reproducing recorded signals.

The operation shown in FIG. 1 will be explained below using the time chart shown in FIG.

The playback speed of the signal (2) extracted from the disc 2 by PUS is detected by the synchronization signal detection circuit 4 and the playback speed detection circuit 5 as a signal with a period corresponding to the synchronization signal and the speed, respectively.

When the playback speed is significantly different from a predetermined speed, such as during startup, the switching control circuit 7 and the switching circuit 6 input the output θ of the playback speed detection circuit 5 to the f-V converter 8.
works.

The output ■ of the switching circuit 6 is the output of the delay circuit 9. Through the pulse generation circuit 10, the switch circuit 17 and the pulse generation circuit 11 are led to the switch circuit 14, and the switch circuit 17.1
0Ny10FF for each of 4'i. Pulse generation circuit 1
A short pulse ■ is generated at the rising point A of 1i1■, and at this time, the switch circuit 14 is closed and the capacitor 13 is connected (
Apply the voltage of the redensor 12.

When the pulse (2) ends, the voltage of the capacitor 13 is held. On the other hand, the output pulse of the pulse generating circuit 10 which has passed through the delay circuit 9 is generated at a point B1 which is delayed from A, and switches the switch 17 to 0)I. At this time, the charge in the capacitor 12 is discharged and the voltage becomes zero. Pulse generator 10
When the pulse (2) ends, the current from the current source 16 is integrated into the capacitor 12, and the voltage (2) increases until the next pulse arrives. Next, the voltage of the capacitor 12 is sampled and held in the capacitor 13 by a pulse generated at a point A by the pulse generating circuit 11.

By the way, when the playback speed falls within the detection range of the synchronization signal detection circuit 4, the switching control circuit 7 drives the switching circuit 6f to switch the speed signal to the output @ side of the synchronization signal detection circuit 4, and the switching control circuit 7 drives the switching circuit 6f to switch the speed signal to the output @ side of the synchronization signal detection circuit 4. Perform speed control.

As explained above, speed control is performed smoothly when the signal is taken out from PU5, but PUs
When the disc 2 is stationary, such as when starting up, the Vi scratch signal cannot be obtained. In this state, a speed signal corresponding to the rotational speed is not obtained, so if speed control is performed, there is a possibility that operations such as reverse rotation and runaway may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a playback speed control device that smoothly controls the speed from standstill to steady rotation.

Therefore, in the present invention, when pulling the motor from standstill to steady rotation, a constant voltage is first applied to rotate the motor, and after a signal is output from the PU, speed control is performed.

FIG. 3 shows an embodiment according to the invention. In FIG. 3, the same reference numerals as in FIG. 1 indicate the same parts as in FIG. 1. 20 is a fixed voltage, 21 is a state discriminator that detects the envelope of the signal and determines whether the PU3 is detecting the signal, and 22 is a switching circuit. Explain using a chart.

When the disc 2 is stationary, the PU 5 cannot read the signal and cannot obtain a reproduction speed signal.

When the switching circuit 22 is connected to the fixed voltage 20 side at t=Q, the fixed voltage 20 is applied to the motor and the motor 1 rotates. When the disk 2 rotates, a signal ■ is taken out from the PU3. At time t=tIK, the signal ■ can be obtained sufficiently, and the output ■ of the state discriminator 21 becomes “Highkk”.
”, and the switching circuit 22 is controlled to select the control signal ■ side based on the speed signal. Here, since the signal ■ is being reproduced, the rotation speed is controlled in the process explained in the conventional example below, and the time At t=tt, the rotation speed is pulled within the synchronization detection range, and the output O of the switching control circuit 7 becomes "Hsh", and stable rotation control based on the synchronization signal is achieved.

FIG. 5 shows another example of the present invention in which the f-V converter 8 is constructed of a digital circuit. Honji 1 (.

In this example, the pulse interval of the speed detection signal is counted, an η wave proportional to the counted value is created, this η wave is smoothed to obtain a voltage proportional to the speed, and this is returned to the controlled object to perform speed control. It is something.

In FIG. 5, the same symbols as in FIG. 3 indicate the same parts. The time shown in Figure 6 below)? The operation shown in FIG. 5 will be explained based on this.

40 is a reference oscillator, 41.42.45.44.47 is a counter, 45 is a latch, 46 is MPX, 50 is an adder,
A phase comparator is composed of a 51-digit Ex-OR, 52 is an η smoothing filter, and 53 and 54 are AND gates. The counters 42, 45 measure the time ta r l! for the output of the switching circuit 6. Output i-delayed signals ■ and o. After being reset by the reset signal @, the counter 41 starts counting with the clock of the reference oscillator 40 and counts the length of the reset signal ■ section. The latch 45 latches the count value of the counter 41 according to the latch signal.

When the MPX46fA side is selected, the counter 47 obtains a count value corresponding to the pulse width of the speed detection signal. Which count value is loaded into the counter 47 and a waste signal O having a data ratio proportional to the count value is generated. By smoothing this W wave, a DC voltage proportional to the playback speed can be obtained. Similarly, a signal o having a constant duty ratio corresponding to a reference power source is generated by a counter 44, and both signals are inputted to an adder 50 to obtain a control voltage for the motor 1.

Furthermore, in this embodiment, phase control is applied to match the rotational speed with high accuracy. This is detected by a phase comparator 51 such as the phase difference t-Ex-on between the speed detection signal and the reference signal, and is fed back to the motor 1 to be controlled via an adder 50'fr. .

Since the signal ■ is not detected at the time of startup, the output ■ of the status discriminator 21 becomes 'Low'.
The fixed data on the side is selected, and the counter 47 outputs a pulse signal O having a constant data ratio. On the other hand, the output 51 of the phase comparator is 14ND on the switching circuit output side.
Since the gate 54 is gated, the duty ratio is also constant. From this, a predetermined voltage is applied to the motor 1 at the output of the planer 50, and the disk 2 begins to rotate.

Time 1=1. Then, the signal ■ is detected and the state discriminator 2
When the output of 1 becomes 1H#, the MPX 46 switches from B to A side data, and the gate 54 also turns ON), which is the predetermined operation when the signal is detected. The rotation speed is controlled through the process shown in the conventional example.

In this embodiment, at startup, the speed detection signal O1 and the reference signal oF
i duty 50%, phase comparison signal duty 50
A certain amount of electricity is obtained as a percentage.

There are several ways to do this, such as setting O and 0 to the "Low" level and setting only ■ to a data rate of 50%.
An arbitrary duty ratio can be obtained using the fixed data 46 and the reference input waveform of the phase comparator 51.

When the f-V converter 8 is configured with a digital circuit as described above, a fixed voltage generator becomes unnecessary and the circuit can be simplified. Furthermore, AND gate 530 control input terminal S
When i is set to Low, the output of all AND gates 53 is -
"Low", the output of the adder 5o becomes zero. In this way, stop, start, and steady rotation control can be easily performed using the digital circuit.

FIG. 7 shows another embodiment of the present invention. The same reference numerals as in FIG. 5 are the same.

FIG. 8 is a time chart for explaining the operation of FIG. 7. This will be explained below using the diagram.

The state discriminator 21 checks the operation of the pickup 3. A signal is engraved in a spiral on the disk 2, and the pickup 3 traces over this signal string to extract the signal (2). Generally, the vertical direction (focusing direction) and horizontal direction (tracking direction) of such a pickup SFi are controlled so that the pickup 3 correctly traces the signal and reads the signal. . This situation is shown in FIG. 8, the focus control signal [F] and the track control signal O.

At time t = tt, the focus servo is turned on and the pickup 5 reads out the signal (2), but the signal cannot be read out correctly yet because the track control is not applied. At t=tj, the track servo (M) is activated to trace the signal train correctly.The signal ① becomes a normal waveform.Since the focus and track control operate correctly, the status discriminator 21 detects the signal ①. It is determined that the data has been read from the disk 2, and the output (2) is set to Hsh'', the f-V converter 8 and the AND gate -54 are activated, and the switching output (2) is input to control the rotation of the disk 2.

As explained above, the fifth discrimination means of the state discriminator is
In addition to detecting the envelope of the signal ■ explained in the figure,
This can also be achieved using the pickup 50 control signal.

As described above, according to the present invention, it is possible to eliminate the problem of abnormal operation of the reproduction speed control circuit at the time of startup. Furthermore, by providing the control output that is fed back to the motor as a digital signal, the rotation control circuit can be simplified.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional playback speed control circuit, Figure 2 is a time chart diagram of Figure 1, Figure 3 is a block diagram of an embodiment of the present invention, and Figure 4 is a block diagram of a conventional playback speed control circuit. time chart diagram,
5 is a block diagram of another embodiment of the present invention, FIG. 6 is a time chart diagram of FIG. 5, FIG. 7 is a block diagram of another embodiment of the present invention, and FIG. 8 is a block diagram of another embodiment of the present invention. It is a time chart figure. 1...Motor 2...Disk 5.
...Pickup 4...Synchronization signal detection circuit 5...Playback speed detection circuit 6...Switching circuit 8
...fV converter 21...discrimination circuit 41
, 424!To 14 47...Counter 46...MP
X50...Adder 51...Phase comparator 52...Smoothing filter 55.54...A
ND gate f, 1st turn 5th ↓X-2゜

Claims (1)

[Scope of Claims] 1. A plurality of speed detectors and a fixed voltage generator that perform speed detection corresponding to the playback speed based on signals read from a recording medium by a readout device. A switching circuit that selectively selects the outputs of the plurality of speed detectors and the fixed voltage generator, and the state of the playback speed? A reproduction speed control circuit is provided with a state determination W that generates a control signal for determining and switching the switching circuit according to the determination result, and returns the output of the switching circuit to the control target, and when starting, a fixed voltage is applied for a certain period of time. A playback speed control device, characterized in that the voltage is applied to the controlled object, and the first one of the outputs of the plurality of speed controllers is selected during periods other than when waiting for startup. 2. The speed detector consists of a speed detection circuit and a phase detection circuit, and the speed voltage converter of the speed detection circuit and the phase voltage converter of the phase detection circuit are configured with digital circuits, and the speed detection circuit and the phase detection circuit are configured at the time of startup. The configuration is such that the sum of the outputs of the phase detection circuit becomes a predetermined voltage, and after a predetermined time elapses,
2. The playback speed control device according to claim 1, wherein said speed detection circuit and said phase detection circuit are controlled to perform predetermined operations. 3. The playback speed control device according to claim 2, wherein the outputs of the detection circuit and the phase detection circuit are gated by a gate circuit to set the digital output to a "Low" level and stop the controlled object.