JPH0546029B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a motor playback speed control device for smoothly bringing the signal playback speed of a signal playback device for digitally recorded disks, tapes, etc. to a target speed.

When recording digital information on a recording medium such as a disk or tape, a synchronizing signal is generally added, this synchronizing signal is detected during reproduction, and the reproduction speed is controlled so that the period of this synchronizing signal is constant. As an example of this, FIG. 1 shows a block diagram of a playback speed control circuit of a PCM disk playback device. In Fig. 1, 1 is a motor, 2 is a disk, 3 is a pickup (hereinafter referred to as PU), 4 is a synchronous signal detection circuit that detects a synchronous signal from among the signals picked up by PU 3, and 5 is another playback circuit. This is a speed detection circuit.
Here, the playback speed detection circuit 5 is used when the playback speed of the device exceeds the detection range of the synchronization signal detection circuit 4, and detects a unique signal, such as the longest pulse, in the signal extracted by the PU3, and operates normally. This is a speed detection circuit that predicts the synchronization signal period by multiplying this detected pulse width by N times by a multiple N determined by the ratio of synchronization signal period/longest pulse width. 6 is a switching circuit, 7 is a switching control circuit, and 8 is a frequency-voltage conversion circuit (hereinafter referred to as a -V converter).
, constant current source 16, delay circuit 9, pulse generation circuits 10, 11, integrating capacitor 12, switches 14, 1
7 and a hold capacitor 13.
15 is a drive circuit for the motor 1, and 19 is a digital processing circuit for reproducing recorded signals.

The operation shown in FIG. 1 will be explained below using the time chart shown in FIG. 2.

The playback speed of the signal ◯B taken out from the disk 2 by the PU 3 is detected by a synchronization signal detection circuit 4 and a playback speed detection circuit 5 as a signal with a period corresponding to the synchronization signal and the speed, respectively.

When the playback speed is significantly different from the predetermined speed, such as when starting up, the output of the playback speed detection circuit 5 is set to -
Switching control circuit 7 to input to V converter 8
And the switching circuit 6 operates.

The output of the switching circuit 6 is led to the switch circuit 14 via the delay circuit 9, the pulse generation circuit 10, the switch circuit 17 and the pulse generation circuit 11,
Switch circuits 17 and 14 are turned on and off, respectively. The pulse generating circuit 11 generates a short pulse ○ at the rising point _A1 of ○, and at this time the switch circuit 1
4 is closed and the voltage of capacitor 1 is applied to capacitor 13. ○When the pulse ends, capacitor 1
3 voltage is held. On the other hand, the output pulse of the pulse generating circuit 10 which has passed through the delay circuit 9 is generated at point _B1 , which is delayed from _A1 , and turns on the switch 17.
At this time, the charge in the capacitor 12 is discharged and the voltage at ○chi becomes zero. When the pulse from the pulse generator 10 ends, the current from the current source 16 is integrated into the capacitor 12, and the voltage at ○chi increases until the next pulse comes. Next, the voltage of the capacitor 12 is sampled and held in the capacitor 13 by the pulse generated at the point _A2 by the pulse generating circuit 11.

By the way, when the playback speed falls within the detection range of the synchronization signal detection circuit 4, the switching control circuit 7 drives the switching circuit 6 to switch the speed signal to the output ○○ side of the synchronization signal detection circuit 4, and based on the synchronization signal Performs speed control.

As explained above, speed control is performed smoothly when the signal is being taken out from PU3, but when the PU3 is unable to take out the signal, for example when the disk 2 is stationary such as during startup, no signal can be obtained. . In this state, a speed signal corresponding to the rotational speed is not obtained, so if speed control is performed, there is a possibility that operations such as reverse rotation or runaway may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a playback speed control device that smoothly controls the speed from standstill to steady rotation.

Therefore, in the present invention, when pulling the motor from standstill to steady rotation, a constant voltage is first applied to rotate the motor, and after a signal is obtained from the PU, speed control is performed.

FIG. 3 shows an embodiment according to the invention. In FIG. 3, the same reference numerals as in FIG. 1 indicate the same parts as in FIG. 1. 20 is a fixed voltage, 21 is a state discriminator that detects the envelope of the signal and determines whether the PU 3 is detecting a signal, and 22 is a switching circuit.

The operation shown in FIG. 3 will be explained below using the time chart shown in FIG.

When the disk 2 is stationary, the PU 3 cannot read the signal and cannot obtain a reproduction speed signal.

When the switching circuit 22 is connected to the fixed voltage 20 side at t=0, the fixed voltage 20 is applied to the motor 1 and the motor 1 rotates. When disk 2 rotates
Signal ○A is taken out from PU3. Time t=
At _t1 , the signal ○I can be sufficiently obtained, the output ○nu of the state discriminator 21 becomes "High", and the switching circuit 22 is controlled to select the control signal ○ri side based on the speed signal. Here, since the signal ○A is being regenerated, the rotation speed is controlled in the process explained in the conventional example below, and at time t= _t2 , the rotation speed is pulled within the synchronization detection range, and the output of the switching control circuit 7 ○D becomes “High” and stable rotation control is performed based on the synchronization signal.

FIG. 5 shows another embodiment of the present invention in which the -V converter 8 is constructed from a digital circuit. In this example, the pulse interval of the speed detection signal is counted, a PWM wave proportional to the counted value is created, this PWM wave is smoothed to obtain a voltage proportional to the speed, and this is fed back to the controlled object to perform speed control. It is something to do.

In FIG. 5, the same symbols as in FIG. 3 indicate the same parts. The operation shown in FIG. 5 will be explained below based on the time autograph shown in FIG. 6.

40 is a reference oscillator, 41, 42, 43, 44,
47 is a counter, 45 is a latch, 46 is MPX,
50 is an adder, 51 is a phase comparator composed of Ex-o _R , 52 is a PWM smoothing filter, 53, 5
4 is an AND gate. The counters 42 and 43 output signals delayed by times t _a and t _b with respect to the output ◯ of the switching circuit 6 . After the counter 41 is reset by the reset signal, the reference oscillator 40
It starts counting with the clock of 1 and counts the length of the reset signal section. Latch 45 latches the count value of counter 41 in response to a latch signal. MPX46
When A side is selected, the counter 47 obtains a count value corresponding to the pulse width of the speed detection signal. This count value is loaded into the counter 47, and a PWM signal having a duty ratio proportional to the count value is generated. By smoothing this PWM wave, a DC voltage proportional to the playback speed can be obtained. Similarly, a signal having a constant duty ratio corresponding to a reference power source is generated by a counter 44, and both signals are input to an adder 50 to obtain a control voltage for the motor 1.

Furthermore, in this embodiment, phase control is applied in order to match the rotational speed more precisely. This detects the phase difference between the speed detection signal O and the reference signal using a phase comparator 51 such as Ex- _OR , and feeds it back to the motor 1 to be controlled via an adder 50.

Since the signal ○a is not detected at the time of startup, the output ○nu of the state discriminator 21 becomes "Low". MPX
46, fixed data on the B side is selected, and the counter 4
7 outputs a pulse signal with a constant duty ratio. On the other hand, the output 51 of the phase comparator similarly has a constant duty ratio because the switching circuit output ◯◯ is gated by the AND gate 54. From this, a predetermined voltage is applied to the motor 1 at the output of the adder 50, and the disk 2 starts rotating.

At time t= _t1 , the signal ○a is detected, the output ○nu of the status discriminator 21 becomes “High”, and the MPX46
is switched from data on the B side to data on the A side, and the gate 54 is also turned ON, resulting in a predetermined operation when a signal is detected, and the rotational speed is controlled in the process shown in the conventional example.

In this embodiment, at startup, the speed detection signal and the reference signal have a duty of 50%, and the phase comparison signal has a duty of 50% to obtain a predetermined voltage. There are several ways to do this, such as setting the and to "Low" level, and only setting the duty to 50%.
An arbitrary duty ratio can be obtained using the fixed data of the MPX 46 and the reference input waveform of the phase comparator 51.

As explained above, when the -V converter 8 is configured with a digital circuit, a fixed voltage generator becomes unnecessary and the circuit can be simplified. Furthermore, when the control input terminal S ₁ of AND gate 53 is set to “Low”, all
The output of the AND gate 53 becomes "Low" and the output of the adder 50 becomes zero. In this way, stop, start, and regular rotation control can be easily performed using the digital circuit.

FIG. 7 shows another embodiment of the present invention. The same reference numerals as in FIG. 5 are the same.

FIG. 8 is a time chart for explaining the operation of FIG. 7. This will be explained below using the diagram.

The status discriminator 21 checks the operation of the pickup 3. A signal is engraved in a spiral on the disk 2, and the pick-up 3 traces over this signal string to extract the signal ○I.
Generally, such a pick-up 3 is controlled in the vertical direction (focus direction) and horizontal direction (tracking direction) so that the pick-up 3 correctly traces the signal and reads the signal. . This situation is shown in FIG. 8, which shows focus control signals and track control signals.

At time t=t _i , the focus servo is turned on and the pick-up 3 reads out the signal ○, but since the track control has not been performed yet, the signal cannot be read out correctly yet. At t=t _j , the track servo is turned on and the signal train is traced correctly, and the signal ○a has a normal waveform. As the focus and track control have operated correctly, the status discriminator 21 determines that the signal ○a has been read from the disk 2, and sets the output ○nu to "High" to turn on the -V converter 8 and the AND gate 54. The switching output ○ho is inputted as active, and the rotation of the disk 2 is controlled.

As explained above, the discriminating means of the state discriminator can be realized by using the control signal of the pickup 3, in addition to detecting the envelope of the signal ◯ and ◯ as explained in FIG.

As described above, the present invention can eliminate the problem of the playback speed control circuit operating abnormally at startup. Furthermore, by providing a control output that is fed back to the motor as a digital signal, the rotation control circuit can be simplified. Also, separately from the rotation speed detection circuit of the motor (separately from the rotation speed detection), a state determination circuit is used to determine the state by detecting the envelope or the focus control signal and the track control signal. Therefore, the fixed voltage is set only when it detects and confirms that the signal is starting to play correctly, i.e., when the motor starts rotating and the pickup starts correctly tracing the disk track. The function can be made to switch from the supplying startup circuit side to the playback speed control circuit side. Therefore, the transition from the startup state to the correct regeneration state is performed safely and reliably, and steady rotation can be achieved more stably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional playback speed control circuit, FIG. 2 is a time chart of FIG. 1, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG.
5 is a block diagram of another embodiment of the present invention. FIG. 6 is a time chart of FIG. 5. FIG. 7 is a block diagram of another embodiment of the present invention. The figure is a time chart of FIG. 7. 1...Motor, 2...Disk, 3...Pickup, 4...Synchronization signal detection circuit, 5...Playback speed detection circuit, 6...Switching circuit, 8...-V
Converter, 21...Discrimination circuit, 41, 42, 43,
44, 47...Counter, 46...MPX, 50
... Adder, 51 ... Phase comparator, 52 ... Smoothing filter, 53, 54 ... AND gate.

Claims (1)

[Scope of Claims] 1. A plurality of speed detectors that detect a speed corresponding to a playback speed based on a signal read out from a recording medium by a reading device, a fixed voltage generating means, a plurality of speed detectors, and a fixed voltage generating means. A state in which a switching circuit selectively selects the output of the fixed voltage generating means and an envelope detection output of the signal read by the readout device determines the state, and a switching control signal according to the determination result is output to the switching circuit. and a discrimination circuit, the playback speed control device is configured to feed back the output of the switching circuit to the controlled object, wherein at startup, the state discrimination circuit causes the fixed voltage generated by the fixed voltage generating means to be set to the control target. The switching circuit is controlled so that the signal is applied to the target, and when the state determining circuit determines that the signal read out by the pre-reading device after activation has started to be correctly reproduced, the state determining circuit controls the switching circuit. A playback speed control device characterized in that one of the outputs of the plurality of speed detectors is applied to the controlled object. 2. A plurality of speed detectors that detect a speed corresponding to a playback speed based on a signal read out from a recording medium by a reading device, a fixed voltage generating means, and outputs of the plurality of speed detectors and the fixed voltage generating means. determining the state of the readout device by detecting the focus control signal and the track control signal of the readout device;
A playback speed control device comprising: a state determining circuit that outputs a switching control signal to the switching circuit according to a determination result, and configured to feed back the output of the switching circuit to a controlled object, wherein the state determining circuit is configured to feed back the output of the switching circuit to a controlled object; A circuit controls the switching circuit so that the fixed voltage generated by the fixed voltage generating means is applied to the controlled object, and determines the state when the signal read out by the reading device starts to be reproduced correctly after activation. A playback speed control device, characterized in that, when the state is determined by a circuit, the switching circuit is controlled by a state determining circuit so that one of the outputs of the plurality of speed detectors is applied to the controlled object. 3. The speed detector is composed of a speed detection circuit and a phase detection circuit, and the speed voltage converter of the speed detection circuit and the phase voltage converter of the phase detection circuit are configured with digital circuits, and when starting, the speed detection circuit and the phase detection circuit are connected. The phase detection circuit is configured to operate as the fixed voltage generating means so that the sum of the respective outputs becomes the fixed voltage, and after a predetermined time period has elapsed during which the signal can be read out from the recording medium by the reading device,
3. The playback speed control device according to claim 1, wherein the speed detection circuit and the phase detection circuit control the speed and phase of the controlled object. 4. The playback speed control device according to claim 3, wherein the outputs of the speed detection circuit and the phase detection circuit are gated by a gate circuit to set the digital output to a "Low" level and stop the controlled object.