JPS58209291A - Remote monitor controlling system - Google Patents

Abstract

PURPOSE:To obtain high response speed and wide range of use, by connecting plural microprocessor units with a common bus in order to make a constitution which performs a data exchange between the processor units. CONSTITUTION:When a subprocessor unit SIF receives a data from an opposite station or when it receives the output of a main processor unit MPU, it outputs a common bus use right requesting signal BUSR, and the unit MPU gives a common bus use authorizing signal BUSA to the unit SIF, if the common bus is not being used, to open the bus. The unit SIF given the bus use right directly accesses a system memory (RAM or ROM) to carry out a DMA transfer for exchanging a data. When the bus use request is resetted after the completion of exchange of whole data, the unit MPU immediately secures the bus to continue processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an S-P/
This invention relates to a remote monitoring and control system using Sobetsu's microprocessor unit for a P-8 conversion unit, a host computer, a data transfer unit, a digital input/output control unit, and the like.

Microcomputer systems are also used in conventional remote monitoring and control equipment, but all operations are controlled by a single CPU, and data exchange with each person's blade section is executed by simple commands. In this case, the CPU performs logical operations or edits on the data while providing services to each input/output port, and runs the respective drivers for the ports prepared for each opposing device or terminal. Depending on the responsiveness and processing capacity required of the system, the CPU may become overloaded.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel remote monitoring and control system that reduces the load on the main processor unit, has high response speed, high functionality, and is highly versatile. Our goal is to provide the following.

According to the present invention, the operation/failure status information of the scattered monitored control stations is centralized to perform monitoring control in real time, and each processor unit accesses the system memory via a common bus and exchanges data. By adopting a multi-processor method, signals can be transmitted using any communication format without changing the hardware, and functions can be distributed to each processor unit, reducing the load on the main processor unit and achieving high response speed. ,
A highly functional and highly versatile remote monitoring and control system can be obtained.

The present invention applies individual microprocessor units to each control section such as an S-P conversion section, a p-s conversion section, a data transfer section with a host combiator, and a digital signal output section for monitoring control items, and exchanges data. Because the system memory is used as a medium for memory read/write commands, the main processor unit does not directly intervene in conventional port services, and only manages data on the memory.
Communication processing with the same station or host computer and input/output of supervisory control items are executed by sub-processor units assigned to each function, thereby reducing the load on the main processor unit. Furthermore, in order for the main processor unit and each sub-processor unit to share one bus and access memory for data exchange,
Switch bus usage rights. This timing is triggered by a phase pulse output from the bus switching timing pulse generation circuit, and control is performed so that a plurality of processor units do not use the bus at the same time.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings. Fig. 1 is a block diagram showing an embodiment of the present invention. In the figure, sub-processor units 5IFI to 5I
Fn is a P-8/S-P converter that transmits and receives supervisory control data in the communication format of the opposite station device, and the processing program in the communication format is loaded from the area designated by the main processor unit MPU at system startup.

A loader for loading this program is stored in the ROM K I built in each SIF, but it is also possible to make this ROM area thicker and add the processing program to the ROM of each SIF in advance. S I F'1 receives the communication format of the Institute of Technology, performs an error check, and if normal, sets all the received data in the RAM area determined for each opposing station, and sends the message given to each subprocessor. Set the area bit to “ON”,
An interrupt signal is output to notify the main processor (22) MPU of this fact. When the main processor unit MPU that is executing a process receives an interrupt signal, it temporarily suspends the process, outputs an interrupt confirmation signal, checks the bits in the message area, determines the priority, and then interrupts the process that is currently being executed. If the priority is high, the process caused by the interrupt is performed, and if it is low, the previous process is continued.

To edit the received monitoring data and transfer it to the host computer, the main processor unit MPU sets the data in a specified RAM area and sends the identification code using an output command with the hardware code of the sub-processor unit 5IFn+1. Outputs (control code, data area start address, number of data). When 5IFn+1 receives the identification code, it analyzes its contents and takes in the transfer data from the RAM area.
Output to the host computer. All such data exchange between the main processor unit and the sub-processor unit is based on DMA.

Now, since we share one bus and exchange data,
Main processor unit MPU and each sub-processor unit 5IFI-5IFn cannot use the bus at the same time. Usually main processor unit M
The PU monopolizes the bus and uses system memory (Rop, q
, RAM) f and is in charge of the main processor unit) MP'[J. It centrally manages the operations of the device, such as fence calculations, data collection, and data output commands to sub-processor units 5IF1 to 5IFn.

The sub-processor unit SIF outputs a bus service request when receiving data from the opposite station or when receiving an output command from the main processor MPU. If the main processor unit MPU does not output a bus use disallow signal and no other subprocessor unit is already using the bus, the subprocessor unit that outputs the use request is given the right to use the bus, and the main processor unit 6,
MPU releases the bus.

The sub-processor unit that has been given the right to use the bus directly accesses the system memory IJ (RAM or ROM) and performs DMA transfer to exchange data, and when the bus use request is reset after all data has been exchanged, the sub-processor unit immediately accesses the system memory IJ (RAM or ROM). Processor unit) MPU secures the bus and continues processing.

As explained above, the present invention connects a plurality of microprocessor units through a common bus and uses system memory that each processor unit can directly access as a medium for data exchange between the processor units. Since the load on the main processor unit can be easily performed and the load on the main processor unit can be reduced, it is effective in realizing a remote monitoring device that is smaller in size, has higher response speed, functions, and versatility.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. MPU... Main processor unit, S engineering F
1 to 5 IFn...22 sub processors) (S
-P/P-8 converter), 5IFn-1-x...
・Line connector with host computer, RAM...
・Random access memory, ROM...Read only memory, %...Digital input/output device for monitoring control items, DTsT...Common bus switching timing phase pulse generator, DISP... ...Monitoring control panel, BUSR...Common bus usage right request signal,
BUSA...Common bus use permission signal, BSD1
~BSDn+2...Common bus switching timing phase pulse. Patent Applicant: NEC Co., Ltd. Representative Patent Attorney Yutabe Kumagai No. 1 Hibiki Proceedings Amendment June 28, 1980 Commissioner of the Patent Office Kazuo Wakasugi - 7 1 Indication of Case 1989 Patent Application FA93410 No. 2 Title of the invention: Remote monitoring and control system 3 Relationship with the case of the person making the amendment Patent applicant address: 33-1 Shibahyaku-chome, Minato-ku, Tokyo Name (42)
3) NEC Corporation Representative President Tadahiro Sekimoto 4 Agent Address Kumagaya Patent Office 2215-22 Kurihara, Zama City, Kanagawa Prefecture Telephone 0462 (56) 2956 / (53) 8499 - Brief explanation of the drawings of the specifications Column 6 Contents of amendment 1, "Ruro" on page 8, line 10 of the specification of the present application has been replaced with "%"
” he corrected.

Claims (1)

[Claims] In remote monitoring and control systems that perform centralized monitoring and control by connecting one or more remote monitoring and control devices, S-P conversion, p-s conversion of monitoring or control signals, editing and input/output of monitoring/control data, and upper-level combinator A system in which one main processor unit and a plurality of sub-processors share and execute functions such as sending and receiving data to and from the system, each processor unit is connected to a common bus, and each processor unit can access the system. A remote monitoring and control system characterized by having a bus switching timing pulse generation circuit that exchanges data between the respective processor units using a memory as a medium and assigns the right to use the common bus to each of the processor units.