JPS58207711A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To make the titled circuit operatable at a high frequency, by controlling a toggle signal with an output signal. CONSTITUTION:When a toggle enable signal TE is ''0'', an input signal of a transmission gate TG25 is ''0'' level and an input signal of a TG26 is ''1'' level since the TE signal is an inversion of TE signal inverted at an inverter 31. In this state, a feedback signal is controlled by switching the outputs Q, Q' of the FF circuit depending on the output state of the outputs Q, Q'. That is, when the output Q is ''1'' level, the TR25 is conductive and the TG26 is nonconductive. When an input signal ''0'' level of the TG25 is fed back and the output is ''0'' level, the TG25 is nonconductive and the TG26 is conductive, and the binary count mode is realized by feeding back the input signal ''1'' level of the TG26.

Description

[Detailed description of the invention] The present invention relates to a toggle type flip 7p tube circuit.

FIG. 1 is a block diagram of a conventionally used toggle type seven lip-flop circuit in which an output feedback circuit is controlled by a toggle signal. In the figure, transmissions N7'f-) ('1''G) 1 to 6 consisting of a P-channel M08 transistor and an N-channel MO8) transistor, and a Pf-channel MO8 transistor and an N-channel MO8 transistor are shown.
8) Inverter circuits 7 to 14 made of transistors are used.

Gate 1 is a data read transmission gate, and gate 4 is a transmission gate that operates when holding data.

The toggle type flip-flop circuit shown in Fig. 1 is based on a D-type master-slave type flip-flop circuit.
Toggle enable signal (TI) to output Q, Q feedback circuit
are using. Iggle enable signal TI is I □
When the output is at L level, the output Q is selected in the feedback circuit, and in synchronization with the clock signal, the transmission gates 1 to 1 are selected.
4 is conductive and non-conductive. When the clock signal OL is 'lol level, the transmission gate 1 becomes conductive and reads the output signal 4 as data, and when the clock signal is 11w, the transmission gate 3 becomes conductive and outputs the data. In this way, when TE is at the 119I level, this F/F operates as a binary counter. Next, when TI is at Ill level, Q is selected as the feedback circuit. The selection of Q is the same as the data read by the lithic operation and the output data of this flip-flop circuit, so the output changes frequently and is a toggle-type flip-flop circuit that holds the data of the slave. It is. The feedback circuit of this flip-flop circuit has outputs Q, Q
is used as TG's 5,60 input data. T.G.
The input capacitance of is mainly a junction capacitance, which is generally larger than the input gate capacitance. Inverter 9
The load capacitance is the sum of the wiring capacitance + the input gate capacitance of the inverter 1o + the input capacitance of the TG6. Also, in binary count mode, the on resistance of %TG6 and 'j
``The sum of the output capacitance of G5 and 6 and the input capacitance of TGI results in a large load.This large load increases signal delay and affects the operating frequency, making it impossible to operate at high frequencies. there were.

This invention was made in consideration of the above circumstances, and its purpose is to provide a toggle type flip-flop circuit that can operate at a high frequency. Detailed explanation of. Second
The figure shows one embodiment, and 21 to 26 are transmission gates, and 27 to 33 are inverter circuits. Figure 2 is similar to Figure 1 except for the feedback circuit,
Basically, a D-type master-slave type flip 70-tube circuit is used, and the feedback circuit section uses two transmission gates as in FIG. Since the input characteristic equation of this circuit is TE-Q+TE.Q, the circuit configuration is such that the gate control signal and input signal are completely reversed from those of the feedback circuit shown in FIG. With this circuit configuration, the load capacitance of the inverter 9, which is a problem with the circuit configuration of FIG. 1, becomes as follows by using the circuit configuration of FIG. 2. This is the sum of the 300 Å gate capacitance of the I/verter, the N-channel side input gate capacitance of TG25, the P-channel side input gate capacitance of TGII, and the wiring capacitance. The same holds true in the binary count mode, and the load capacity of the inverter 9 in FIG. 1 is clearly reduced compared to that of the inverter 9 shown in FIG. 1, making it possible to operate at a higher frequency. The circuit operation will be explained with reference to FIG. When the TFf signal is Iol, the input signal of the TG 25 is at the f□f level, and the input signal of the 'I'G 26 is a signal inverted by the 'B times signal inverter 31, so it is 11 levels. In this state, the feedback signal is controlled by switching depending on the output state of the outputs Q and Q of the flip-flop circuit. That is, the output Q is I
+ 1 @When level, FG25 becomes conductive and T
G26 becomes non-conductive. TG25 input signal eog
Return the level and output again. When T is at “θ” level, T
O25 becomes non-conductive, 'I'G26 becomes conductive, and '['026 input (No.N "1" level is fed back to realize binary count mode. Also, T
l! When i is 1 level, the input signal of ↑G25 is 81@
level, and the input signal of '['G26 becomes 1o'' level.

At this time, when the output Q is at the 11@ level, 'I' (125 becomes conductive, TG26 becomes non-conductive, 111 lvl is fed back and does not change even if the count operation is performed. Also, the output Q is at the "0" level. Originally, "I'G25 becomes non-conductive and "I'G26" becomes conductive, and the "O" level is returned, and the output state line does not change even if a count operation is performed.

As explained above, according to the present invention, it is possible to provide a toggle type 7-lip, 7-p tube circuit that can operate even at high frequencies. Even if this circuit configuration has a reset function or a set configuration, the basic operation is the same, so although the operation is omitted, it is clear that the same effect is obtained.

[Brief explanation of drawings]

FIG. 1 is a conventional toggle type flip 7-day circuit diagram, and FIG. 2 is a water-free circuit according to an embodiment of the present invention. Explanation of symbols for main parts 1-6. 21-26 are transmission gates (TO) 7-14 in which P-channel MO8) transistors and N-channel MO8) transistors are connected in parallel. 27-33 are 0M0S inverter circuits, OLK is a clock input terminal, OL is in phase with OLK, and OL is in opposite phase. Ti is a toggle enable terminal, TE is in phase with T and E, and ri is a signal with opposite phase. F Tobi 7 Figure θ Z, r Figure

Claims (1)

[Claims] A flip-flop circuit that enables high-speed operation of the circuit by controlling the toggle signal with the output signal in the feedback circuit section of a toggle flip-flop logic circuit that feeds back an output signal and uses it as an input signal.