JPS58207149A - Comparator - Google Patents

Abstract

PURPOSE:To perform a comparison of data with combinations of prescribed timing signals and without using a complicated comparison timing signal generating circuit, by applying the timing signal to a part of the address of a memory when plural comparison data are supplied to said address. CONSTITUTION:An inspection data generated from an inspection data generating circuit 11 is supplied to a multiplexer 13 together with a data to be inspected which is generated from a generating circuit 12 for data to be inspected. One of these two data is selected by the control of a switch signal 18 and supplied to a memory 10 via an address bus 16. At the same time, a write data 20 is fed to a data bus 17 via a write buffer 15 and then written to the memory 10 by a write control signal 19. Then the write signal 20 is applied to the memory 10 in the form of a timing signal. The coincidence is obtained between the inspection data and the data to be inspected with combinations of prescribed timing signals and without using a complicated comaprison timing signal generating circuit. Then plural data are compared with each other, and the result of comparison is added to a latch 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit, and more particularly to a comparison circuit having a function of comparing a plurality of data and detecting a match.

Conventional '4! The 1g4 sweetfish that compares the number of data is the part that performs the comparison between the main VC inspection data and the plate horizontal inspection data, and the part that generates the timing signal to compare these data? The book was completed. Therefore, algebraic data comparison JF ~
Due to a number of issues, the Q comparison 1 (requires an extremely complicated...Dounia structure), and the cost and production were quite disappointing.

FIG. 1 is a schematic block diagram of comparison path (9) that has been proposed in the past. In the figure, reference numeral 1 denotes a launch circuit for holding data to be inspected, into which data to be inspected is written from the alternative inspection data generating circuit 2. The data to be inspected is compared with the inspection data generated from the inspection data generation circuit 4 in the coincidence detection circuit 3, and the result is sent to the comparison timing signal generation circuit 5.
The result holding circuit 6 is set by the timing signal outputted from the base station. flj, if both data match, data is "1", and if they do not match, data is "0"
is set in the result holding circuit 6, and then output to the controller, etc. In this case, the key point is the timing at which the comparison result is set in the result holding circuit 6. This timing is required depending on the data to be examined, but it is not sufficient if it is generated periodically in a negative cycle. Therefore, the conventional comparison timing signal generation circuit 5 is configured to generate a desired comparison timing signal by combining, for example, four types of timing signals A to D. As a result, a logic circuit for performing logical operations on each timing signal had to be designed in hardware. Moreover, since this circuit can only perform calculations between predetermined timing signals, it has the disadvantage that another circuit is required to generate other comparison timing signals. Furthermore, since these circuits are used only as dedicated circuits for generating comparison timing signals, they lack versatility and also have the disadvantage of occupying a large chip area. Furthermore, in order to perform arithmetic operations on a plurality of keys, the configuration of the logic circuit itself becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a versatile comparison circuit, and in particular, to provide a comparison circuit that can compare a plurality of data with a simple configuration.

The comparison circuit of the present invention includes means for sending data to be compared as an address to an address bus, and n1 connected to this address bus, and matching data is set to an address value where the data to be compared matches the data to be compared. the memory, means for sending data to be compared to the address bus to access the memory, and means for latching data read from the memory.

According to the present invention, by using a memory and supplying the data to be compared and the data to be compared as addresses of this memory, it is possible to determine whether or not the two match based on the data set in the memory. can.

Therefore, a plurality of pieces of data can be compared using the same procedure with a simple configuration, and there is no need to provide a dedicated circuit for each piece of data, so it is extremely versatile.

Note that as a memory, it is possible to use R and OM in which matching data is written in advance, or a RAM that can supply the data to be compared as an address before comparison and write matching data at a desired address value. May be used. It goes without saying that these memories can be used not only for ratio V but also for general program processing.

Furthermore, when data to be compared is supplied to a memory address, if the timing signal w4 is applied to a part of that address, the combination of timing signals of PJT legs can be calculated without using a complicated comparison timing signal generation circuit. A comparison circuit that can compare time data can be created.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit block diagram showing an embodiment of the present invention. In this example, RAMl0 is used as the memory, and this RA
It is assumed that M10 receives a plurality of bits of address in parallel from the address bus 16 and inputs and outputs 1-bit data via the data bus 17. Test data (data to be compared) is output from the test data generation circuit 11, and data to be tested is output from the temporary test data generation circuit 12.

Both data are selected by p multiplexer 13 by 1tilJXI of switch 1g 18, and the selected -1 is input to RAM 10 via address bus 16. Refining data (here we show the comparison results, for example - twin data) 20
is sent to the data bus 17 via the write buffer 15 and transferred to the RAM l0 by the n1 write control signal 19.
be included.

Now, when the test data matches the pre-test data.

An example in which data "1" is set in the latch 14 as a result will be explained. Multiplexer 13 by switching signal 18
outputs @page data to the address bus 16. Test data that needs to match the temporary test data is sent to the address bus 16, and this is used as an address in RAM10.
access.

□ At this time, data "1" is sent to the data bus 17 as write data 20, and rlJk is written to the address. Any number of data may be written.

After writing is completed, move to comparison mode. In the comparison mode, the multiplexer 13 is switched to the data-to-be-tested generation circuit side, and the generated pre-test data is sequentially sent to RAM10 as an address. The RAM10 accessed by this data to be tested reads out the cheater stored in the paired address, but data "0" is latched at addresses that do not match the test data, and only when the data to be tested matches the data to be tested. Data "1" is latched.

As is clear from this explanation, by using a general-purpose memory and giving test data and data to be tested as their addresses, the conventional coincidence detection circuit can be omitted, and the microcomputer The circuit area can be reduced. In addition, multiple matching data can be stored in RAM10.
By storing the data in a file, it is possible to compare multiple pieces of data regardless of the order in which the data to be inspected is generated. Furthermore,
By allowing multiple bits of data to be read out in parallel from RAM10, necessary information other than the comparison results can be read out at the same time.

Further, with reference to FIG. 3, another embodiment of the comparison circuit of the present invention, which can perform comparison processing at arbitrary timing, will be described. A memory (RAM) 25 is connected to a 1'6-bit address bus and to the latch 24 through a 1-bit data bus. The pre-test data consists of 12 bits9, these are address bus A.

~ A 1 H is supplied. Sixteen bits of test data are prepared and supplied corresponding to address buses A0 to A15, respectively. Four timing signals T1 to T4 are supplied from the timing signal generation circuit 23 to the four address buses A12 to A1. Here, the timing signal generating circuit 23 may be one that generates a signal indicating a machine cycle or state, or one that interprets a command and generates its control signal.

These four timing signals are supplied to the memory 20 in data comparison mode. The test data generation circuit 22 outputs data corresponding to 12 bits of data to be tested to the address buses A6-A11.
For A16, the combination data of timing signals with which the pre-test data is actually compared is output. The memory 25 is accessed using these data and data "1" is transferred to the memory location. The write circuit may be the same as that shown in FIG. 2, and will therefore be omitted here.

The data to be inspected outputted in the comparison mode is subjected to a special comparison using a predetermined combination of timing signals.
The result is set in the latch 24 at that timing. Therefore, in this example, 16 types of timing can be set without using a special logic circuit sound for determining the combination of timing signals. In detail, as for the memory configuration, address Ao-Al is connected to the word line, and address A1 is connected to the word line.
If 2 to A 15 are made to correspond to the digit lines, when the data to be inspected and the inspection data match, and at a predetermined timing among the 16 timings, the desired data indicating the comparison result will be transferred to the latch 24. is set to That is,
The inspection data and the data to be inspected can be compared at a predetermined timing to obtain the results.

Note that the timing signal may be supplied to any bit of the address bus, and the output of the memory may be taken out in parallel so that information other than the comparison result can be read.

Further, a ROM in which the comparative grain size is fixed in advance may be used as the memory. At this time, I am concerned about the test data generation circuit.

As stated above, by using the inspection timing as part of the iRAM address, comparison circuits that are difficult to implement in the past, such as complicated timing and multiple data comparisons, can be realized with a simple circuit. . This is very suitable for checking the operation of various microcomputers and debugging data during the development stage of applied products. Furthermore, by using multiple memories, it is possible to compare different types of data, such as microcomputer addresses and data, at the same timing.

[Brief explanation of drawings]

FIG. 81 is a conventional comparison circuit diagram. 1...Plate inspection data latch, 2...Test data generation circuit, discharge...-Several sheet output circuit, 4...
...Inspection data generation circuit, 5...Comparison timing signal generation circuit, 6...Result holding Lg!
4th road. FIG. 2 is a circuit block diagram according to one embodiment of the invention. 10...Memo 1c 11...Good food data generation times, 12...Sampling test data generation times Ayu,
13...Multiplexer, 14...Latch, 15...Buffer, 16...Address bus, 17...Cheese, l
g...Switching signal, 19...Writing motion signal, 20...Writing data. FIG. 3 is a block diagram of a view according to another embodiment of the present invention. 21...Test plaster data generation circuit, 22...
...Inspection data generation circuit, 23...Timing signal generation circuit, 24...Latch, 25...
··memory. , 1・(

Claims (1)

[Claims] 1. A memory in which data to be compared is set as an address and information indicating a comparison result is set at a predetermined position of the address, and means for supplying data to be compared as an address to the memory. , means for retrieving the information read from the memory when the data to be compared matches the data to be compared. 2. means for supplying data to be compared to an address bus; means for supplying all data to be compared to said address bus; a memory connected to said address bus; and a means for supplying said data to be compared to said memory; a means for writing information indicating a comparison result at a predetermined address; and a means for writing information indicating a comparison result at a predetermined address; A comparator circuit comprising means for taking out the information read out of the memory when the information corresponds to the corresponding content. 3. Set the data to be compared as an address and set the specified address l.
a memory in which information indicative of a comparison result is set in a /s value; means for supplying data to be compared as part of an address to the memory; and supplying a timing signal as another part of the address to the memory; and means for reading out the information from the memory acknowledged by a combination of the timing signal and the Jl/M desirability data.