JPS58205991A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize efficient rewriting without causing unbalance between writing and erasing, by performing the rewriting to a non-volatile memory device, which can be rewritten electrically, by the same pulse voltage and pulse width. CONSTITUTION:Writing to a memory element is performed by grounding a base board 21, drain 23 and source 22, by applying high electric potential 20V to two controlling gates 27 and 31, and injecting an electron to a floating gate 25 from an (n+) area 28. Erasing is performed by applying high electric potential 20V to the drain 23 and source 22, and low electric potential 0V to two controlling gates 27 and 31, and discharging the electron to the (n+) area 28 from the floating gate 25. As the result, an efficient rewriting with no unbalance between the writing and erasing can be realized. However, by defining VTO as the threshold of initial state, VTE as the threshold of erasing state and VOR as writing voltage to be applied to the controlling gate, an expression I shall be satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device having an electrically rewritable floating gate, and is particularly concerned with optimizing its writing and erasing characteristics.

[Technical background of the invention and other issues]

A conventionally known nonvolatile semiconductor memory having an electrically erasable floating gate is shown in FIG. Oxide film 2 on P-type 81 substrate χ. A floating gate 3 is provided via a floating gate 3, a control gate 4 is provided above the floating gate 3 via an oxide film 2, and an n drain region 6 and a source region 6 are provided. h., the part 7 of the oxide film between the free gate 3 and the drain region is to the extent that a tunnel current can flow (~200
It is formed to have a thickness of λ) and serves as a rewriting area. In writing to this memory element, the potential VD of the drain region 5 is set to a low potential and the potential of the control gate 4 is set to a high level, and in the rewrite block 7, electrons are injected from the drain region 5 into the floating gate 3 by tunneling. (is performed by a fist), and erasure is performed by the reverse operation.

When configuring a large capacity memory device using the memory elements of the present invention, the memory elements of the present invention are arranged in a matrix, and when the memory elements are exposed, the read voltage VOR is applied to the control gate 3 of only the selected elements, and the drain region A voltage is also applied to 5. Therefore, in the write state, the threshold value (V
TW) is greater than VGR, and the erased state threshold (V'
ri+) must be smaller than Voi+. This situation is shown in Figure 2. Also, for the read voltage VGR "[
Threshold value VTW after enrichment, threshold value VTI after erasure
B is symmetric, i.e. (Vrw-VOR); (Vow-VTg
) is preferable in terms of device reliability. This is because when these levels fluctuate for some reason, the symmetrical case is the most reliable. On the other hand, from the viewpoint of rewriting, it is desirable that the pulse voltage and width applied to the control gate 4 or the drain region 6 be the same for writing and erasing, respectively. By the way, the write-in and erase characteristics of a memory element having the configuration as shown in FIG. l as axis
u (t) −V There is a linear relationship on the r characteristic. Conventionally,
Floating game) Jl: The threshold value VTO when no charge is injected is usually set to ~IV about tW, so as shown in Figure 3, the time required for induction (tw) is , an imbalance occurred in that the time required for erasing (Lm) was short.

[Purpose of the invention]

The present invention has been made based on the above points, and aims to provide a non-volatile semiconductor memory device that eliminates the unbalance between writing and erasing and is capable of efficient rewriting with the same pulse applied voltage and time. .

[Summary of the invention]

The present invention provides a nonvolatile memory device in which electrically rewritable memory elements having a floating gate and a control gate capacitively coupled to the floating gate are integrated in a matrix on a semiconductor substrate. VTO1
When the erased state threshold is VTI and the continuous voltage applied to the control gate is VGR, then l VTO-VGRl < l Van-VTI I
It is characterized by satisfying By making the pulse width 'WeIB of the applied pulse voltage almost equal, the threshold value VTW after writing and the threshold value VTII after erasing exhibit symmetrical characteristics with respect to VGR. Considering only the characteristics, VTO is most efficient when it is perfectly matched to Van, but for other purposes, such as writing when testing memory devices,
In order to check the cell operation when not erasing, it is preferable that v'ro<Van, so (Vi+ +Voi+)/2<VTO<V
By setting the value within the range of 12), it is possible to improve the characteristics without detracting from the spirit of the present invention. The VTO can be controlled by controlling the impurity concentration of the channel portion by ion implantation or other known methods.

[Effects of the Invention] According to the present invention, rewriting of a magnetically rewritable nonvolatile memory device can be performed with the same pulse voltage and pulse width, and characteristics optimized for continuous rewriting can be obtained.

[Embodiments of the invention]

FIG. 5 shows the main structure of a memory element according to an embodiment of the present invention, (al is a plan view, and tbit (c) and (d) are A-A in (a), respectively. ', B-B'
and C-C' cross section. P-type SI group-1j, 2
1, an n+ type source 22 and drain 23 are provided, a floating gate 25 is provided on the channel region between these two regions via a gate insulating film 24, and a gate insulating pIA is provided on the floating gate 25.
The basic structure in which the first control gate 27 is provided via ze remains unchanged from the conventional one. In this example, in addition to the above basic structure,
A separate area is provided for writing and erasing information. That is, the n-type @2B formed continuously with the source 22
is provided adjacent to the channel region, and the floating gate 25 is placed on this n-type axis 28 with a gate insulating film 29 thin enough to cause a tunneling phenomenon. And the first
Apart from the control gate 27, gate insulating films 26 and 3
A second control gate 31 is provided which is insulated by 0 and is coupled to the floating gate 25. Moreover, as is clear from (al and (bl), the floating gate 25 has an offset gate structure with respect to the source 22 and drain 23, that is, it does not cover the entire channel region, and the remaining portion is covered with the first control gate 21. That is, a part of the control gate 27 of '@1 and the floating gate 26 function as gate electrodes for the successive operation.

Note that gate insulation Ill z 4. z 6 and 30
For example, the gate insulating film 29 in the area where writing and erasing operations are performed is a thermal oxide film having a thickness of about 200 Å, for example, to produce a tunnel effect. Further, when arranging these elements in a matrix to form an array, the source 22 and the first control gate 27 are commonly connected in the row direction.
Drain electrode wirings, which are omitted in the figure, are commonly connected in the column direction.

The reason why the floating gate 25 of this memory element is an offset gate is that even if the threshold value under the floating gate 25 becomes 0■ or less due to erasing, it will still remain in the unselected cell, that is, the first control gate 22. This is to prevent a channel current from flowing in a cell where the applied voltage is OV, thereby making it possible to select P/J. And the offset gate @
For example, by setting the threshold value of the channel A-H controlled by the control gate 27 of 1 to 1, the threshold VTI of this memory cell in the erased state becomes 1. Further, the threshold value VTO in the initial state under the floating gate 25 is a fixed potential (for example, OV) at which the second control gate 31 is located.
The voltage VOR is set slightly lower than 5 V so that a channel is formed when the voltage VOR=5 V applied during selective reading is applied to the first control gate 27.

``Writing of this memory element is carried out using the substrate 21, drain 23,
, ground source 22, and two control games) 21.31
This is done by applying a high potential (20 V) to the n cape region 28 and injecting electrons into the floating gate 25. Erasing is performed by applying a high potential (20V) to the drain 23 and the source 22, a low potential (0■) to the two control gates 27 and 31, and releasing electrons from the floating gate 25 to the n+ region 28. At this time, the writing and erasing characteristics are as shown in Figure 6, with a pulse of 10m5, the threshold value VTW after writing is about 9V, the threshold value VTII after erasing is about 1V, and the selected read voltage Van = 5V. The characteristics are symmetrical to .

Therefore, according to this embodiment, there is obtained a nonvolatile memory device that has no imbalance between writing and erasing and is capable of efficient rewriting.

In this embodiment, the case of N channels/channels has been described, but the same applies to the case of P channels/channels. Furthermore, the present invention is applicable to any nonvolatile memory that can be electrically erased, regardless of its configuration. For example, the present invention can be applied to a case where a memory cell is configured by connecting a selection transistor in series with a memory element to provide pit selectivity with one control gate.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the structure of an electrically rewritable nonvolatile memory, and FIG. 2 is a diagram showing transition characteristics of L memory cell δ writing and erasing. FIG. 3 is a diagram showing an example of write and erase characteristics of the memory cell, FIG. 9S4 is a diagram showing an example of write and erase characteristics for explaining the present invention, and FIGS. FIG. 6 is a diagram showing the structure of a memory element according to an embodiment of the present invention, and FIG. 6 is a diagram showing writing, erasing, and erasing characteristics of the same memory element. ... Drain region 25 ... Floating gate 27 ... First control gate 28 ... n+ territory region 3 ... Second control gate Exiting agent agent Patent attorney Takehiko Suzue π1 Figure 2 Figure VG Elementary 3 Figure - Jn (Right 4 Figure 1 - Jn(t) Figure 5

Claims (2)

[Claims] (1) A nonvolatile semiconductor memory device in which electrically 41F weatherproof memory elements having a floating gate and at least one control gate coupled to the floating gate are integrated in a matrix on a semiconductor substrate. In the above memory element, when the threshold value in the initial state is VTii, which is the threshold value in the erased state of VTO1, and VOR is the continuous voltage applied to the control gate 1jiJ, l Vto-VoRl< I Yell-VTg l
A nonvolatile semiconductor memory device characterized by emitting Xo,5. (2) The memory element includes a source and a drain region formed separately from each other on a semiconductor substrate, an impurity I# region of the same 4I electric type formed continuously with the source or drain, and this region. A floating gate continuously formed on the impurity region and the channel region between the source and drain via an insulating film, and first and second control gates provided to be capacitively coupled to the floating gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the storage content is changed by transfer of charge between the floating gate and the substrate by tunneling on the impurity region.