JPS58205313A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To decrease the effect of load on the voltage fluctuation, by arranging a controlling transistor (TR) between emitters of a couple of TRs constituting a current mirror circuit and a power supply and controlling the controlling TR based on a voltage of an output terminal of the mirror circuit. CONSTITUTION:A base of the 3rd TRQ3 is connected to the output terminal of the current mirror circuit and its emitter potential is determined by the voltage at the output terminal. A resistor BA and diode groups D1-Dn are connected between the emitter of the TRQ3 and the power supply, a voltage between the emitter and the power supply is divided and applied to the base of the 4th TRQ4. The TRQ4 decides a current flowing to the current mirror circuit with this base voltage. As a result, even if a potential V1 of an output terminal P2 is fluctuated, the fluctuation in the emitter-collector voltage of the TRQ2 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current mirror circuit suitable for use when the voltage of the load of a current source fluctuates.

The conventional 41111 circuit is shown in Figure 11. In Figure 1, Pl is the first transistor to which the fiber pressure Vcc is applied, Q+ is the first transistor connected in series to the terminal P1, and the base and collector are connected by 9fi to the It is continued. Qt is the first transistor l
It is a second transistor configured as a magnetic current mirror together with Qt, and the base and
are connected to the base and emitter of transistor Q+, respectively. RL is the second transistor Q,
A load, r, connected in series to the current output terminal is a current output terminal.

In the above configuration, the fixed-flowing work of the fixed-flowing work S. Then, the current mirror infant of the above transistor Q+, Q+, that is, both transistors Q1. A current 1 is supplied to @@RL by each emitter rkJ ratio of Qt. For example, in the above configuration, the magnetic potential v at the vibration point P between the collector of the second transistor and the load RL.

When is passively active - the emitter-collector voltage of the transistor Q will fluctuate, so i! will be supplied to the negative #RL due to the base+m modulation effect. Inkaku l is 1:Kiyai V as shown in Figure 2. becomes smaller as it gets higher. In other words, as the emitter-collector m= becomes smaller, the magnetic current kIIJ width ratio h1 decreases and the collector current decreases.

This invention was made to overcome the above drawbacks.
By applying feedback so that the emitter-collector of the pair of transistors for the current mirror does not change due to fluctuations in the magnetic pressure of the load, the influence of voltage fluctuations in the load can be reduced.
The purpose of this invention is to provide a current mirror circuit that hardly receives +.

Hereinafter, one embodiment of the present invention will be explained with reference to the diagram.

FIG. 6 shows an example of a matt error circuit according to the present invention,
The same parts as the first cause are given the same reference numerals τ, and the explanation will be omitted.

In the same figure, Ql is a sixth PNP transistor, and the base of this sixth transistor Q is connected to the collector of the second transistor Q by 1 m, and the emitters of this transistor Q3 are connected to each other. Thou shalt not hold my hand
& is connected to the base of the fourth transistor Q4 through solid diodes D1 to Dn, and the emitter of the fourth transistor Q4 is connected to each emitter of the first and second transistors Q+-Qt. has been done. BA is connected to the base of the fourth transistor IQ and the terminal P1.

In the above-mentioned - configuration, the first and second transistors Q+
, 111iI&, which supplies 4 forces 1 to the load RL by the first-class mirror effect due to Q*, is as described in (2).

Now, let the 43rd and fourth transistors Qs and Q4 between the six terminals ml+: t-t''t'L be VBm, , VBm4, respectively, and the forward direction tM of the diodes D, ~Dn, and the pressure kVrr. Then, the second transistor Q
The emitter-collector function of , is expressed by the following formula.

vuml=7n4 + nV'p VBm4
``'(1) In the above formula, %VgyH, is vl
The resolution was passed without depending on the value of . There is no base modulation effect due to poor excitation of the RL voltage of the load, and as shown in FIG. In addition, terminal P! The first place v1 is vaO
(VBE1+nvD) and the remaining magnetic field of the bias angle BA.

By the way, in the above example, PIIF) transistors were used as the first and second current mirror transistors Q+ -Qm, but they may also be % n p n ) transistors. diodes D1 to Drlz were used, and this diode D.

~Dn may be replaced with a resistor, and in this case, the bias 61 becomes a constant voltage circuit.

As described above, the present invention is capable of providing a current mirror path that is not affected by voltage fluctuations in am by feeding back current to a pair of current mirror transistors.

[Brief explanation of drawings]

Figure 1 is an electrical circuit diagram that eliminates the conventional current mirror circuit;
The figure shows the FA relationship between the load current and the current output terminal magnetic potential in a conventional cycle 'M; Figure 15 shows an example of the current mirror circuit according to the present invention; This is a diagram of the relationship between the negative storm current and the storm flow output terminal level in a 1g circuit. BA...Bias ffi% DI~Dn...Diode, S...Current source, Ql-Qm... Current mirror transistor, Qs...Sixth transistor Q
4...Fourth transistor, RL...Load. In addition, the same reference numerals in the figures refer to the same or corresponding parts. Agent Shin Tameno (one other person) Figure 1 R Figure 2 VOVcc Figure 3 Figure 4 V Vcc

Claims (1)

[Claims] (1) Connect the bases of a pair of transistors and the devices together, short-circuit the collector and base of one transistor, and connect it to a current source, connect the collector of the other transistor to the current output terminal, This current output terminal is connected to the base of the sixth transistor, and the emitter of the sixth transistor is connected to the sixth transistor via *& diodes connected in series to a bias source or a resistor connected in series to a constant current circuit. 4, and the emitter of the fourth transistor is connected to each emitter of the pair of current mirror transistors.