JPS58205226A - Microcomputer incorporating stand-by function - Google Patents

Abstract

PURPOSE:To obtain either mode by a program instruction by dividing a stand-by mode into the 1st stand-by mode and the 2nd stand-by mode wherein, specially, low power consumption is required. CONSTITUTION:When the 1st stand-by mode is indicated by the instruction, a central processing part 3 sends an instruction and a stand-by control circuit 8 sets a stand-by flag 1. The stand-by control circuit 8 sends a halt signal to respective processing part on the basis of the flag and the respective processing part is held in a halt state. Then, the stand-by control circuit 8 sends a clock stop signal to a frequency dividing circuit 2, whose frequency dividing function is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention provides a microcomputer with a built-in standby function, in particular a first standby mode and a clock generation function using an excavation circuit, thereby reducing power consumption. The present invention relates to a microcomputer in which a standby control circuit for generating a second standby mode and a second standby mode for creating a state are mounted on one chip.

(B) Technical Background and Problems One-chip microcomputers have traditionally been provided with a standby mode in which power consumption is reduced compared to the normal operating mode. Therefore, when the microcomputer does not need to do anything special, the standby mode is set.

(c) Object and Structure of the Invention The present invention provides a standby mode as described above, which is divided into a first standby mode and a second standby mode that particularly seeks a low consumption power state, and each of which can be programmed. The purpose is to make it possible to take it by command, and it is a one-chip device.

The purpose is to provide a one-chip microcomputer with a standby control circuit mounted on the top. Therefore, a microcomputer with a built-in no-standby function of the present invention is a microcomputer that has at least an oscillation circuit and a processing section including an arithmetic processing circuit, and the program counter in the processing section ml standby, which holds the address of the instruction to be executed in the current state, stops the operation of the processing section with each register holding information, and stops the supply of clock signals to the processing section with the oscillation circuit operating; A standby control circuit that detects a standby release signal and generates a second standby mode in accordance with a program instruction, which stops the operation of the processing section and also stops the oscillation operation of the oscillation circuit;
The apparatus is characterized in that it includes a standby release circuit that starts supplying the clock signal or activates the oscillation circuit and releases the processing section from a stopped state in response to the first and second standby modes.

This will be explained below with reference to the inside.

(D) Embodiment of the invention FIG. 1 shows a one-chip example to which the present invention is applied:
ye-x--7F) configuration, 2nd degree, 1.827th... An explanatory diagram illustrating an embodiment of control to reach the i mode,
FIG. 3 is a time chart of one embodiment in the first standby mode, FIG. 4 is an explanatory diagram illustrating one embodiment of control related to the second standby mode, and FIG. 5 is a time chart in the second standby mode.・One example time chart in mode, No. 6
The figure shows the main structure of an example of the part related to generation and cancellation of standby mode (- is shown in the figure).

In FIG. 1, 1 is an oscillation circuit that generates a clock, 2 is an outer circuit, and 1- is an oscillation circuit 1.
3 is a central processing unit, 4-digit timer/counter is configured to also function as a timer (described later), 5 is ) (, AM, 6 is l
(, (JM, 7 represents the input/output circuit section.

In the normal operating mode, the clock generated by the excavation circuit l is circumscribed by the circumferential circuit 2. A clock signal having a predetermined frequency is then distributed to the central processing unit 3 and the like. 171, the microcomputer shown in FIG. 1 is configured to execute processing according to a program on the FUM, for example.

Although the present invention is not limited to microcomputers having the configuration as shown in FIG. 1, the following will explain the microcomputer having the configuration as shown in FIG. 1 as an example.

In the present invention, a standby control circuit is mounted on a microcomputer having the configuration as shown in FIG. 1, for example. FIG. 2 explains one embodiment of control related to the first standby mode, in which the symbols l to 7 correspond to those in FIG. 1, 8 is a standby control circuit, and 9 is a standby mode. Represents a release terminal.

As will become clearer when the time chart shown in FIG. A standby 1 flag (described later in FIG. 6) is set at .

Based on this, the standby control circuit 8 issues a HALT signal to each processing section as shown in the figure (2), whereby each processing section enters the halt state. Then, the standby control circuit 8 issues a clock stop signal to the frequency divider circuit 2 as shown in the figure, and
Stops the frequency division function. Note that in the first standby mode, the oscillation circuit l continues to oscillate. In addition, the contents of the program counter (not shown) (address of the next instruction to be executed) when standby mode occurs are saved, and all other registers, flags, status, H, AM, etc. are saved as standby 1 instruction. The runtime state is now maintained correctly.

When canceling the first standby mode, please refer to Figure 2 1.
When receiving the release input as shown in A, the standby control circuit 8 drops the standby 1 flag mentioned above, drops the clock stop signal to the frequency divider circuit 2, and then releases the halt state. The normal processing mode is returned to, and processing is resumed based on the contents of the timer/counter 4 that were saved above.

FIG. 4 shows IMI i! in the second standby mode.
This is to explain one embodiment of control, and the reference numeral l in the figure
79 correspond to FIG.

Figure 5: As will become clearer when referring to the time chart shown in Figure 1, when the second standby mode is specified by the command, the central processing unit 3 issues an instruction as shown in Figure 5, and starts the standby control. A standby 2 flag (described later in FIG. 6) is set in circuit 8. Based on this, the standby control circuit 8 issues a HART signal to each processing section as shown in the figure (3), whereby each processing section enters the HULT state. Then, the standby control circuit 8 issues a clock stop signal to the frequency divider circuit 2 as shown in the figure (■) to stop the division function of the frequency divider circuit 2, and also outputs a clock stop signal to the frequency divider circuit 2 as shown in the figure (■).
An oscillation stop signal is issued to stop the clock generation function by the oscillation circuit l. At this time, the contents of the program counter (address of the next instruction to be executed) at the time of standby mode are saved, and all other registers, flags, status, etc.) are saved. , the state at the time of execution of the AM and standby 2 instructions is maintained correctly.

When canceling the second standby mode, upon receiving a cancel input as shown in FIG. 4, the standby control circuit 8 drops the standby 2 flag described above.

As a result, the standby control circuit 8 (size,
Oscillation 1! :Drops the oscillation stop signal to the Il circuit. At this time, the output from excavation circuit l (/i is supplied to timer/counter 4, which operates as a delay timer and creates a predetermined time delay. This is stopped under the second standby mode. It can be considered that the oscillation circuit that was in the state starts oscillating and buys the time until it becomes stable.When the timer operation by the timer/counter 4 is time-amplified as shown in the figure (■), the standby control circuit 8 drops the clock stop signal to the frequency divider circuit 2, and then releases the above-mentioned halt state.At this time, the contents of the timer/counter 4 saved above are set in the counter 4, and processing is restarted. .

FIG. 6 shows the main structure of an embodiment of a portion related to generation and cancellation of standby mode. Codes 1 and 2 in the diagram
．． 4.8 corresponds to FIG. 2 or FIG.
3 is a standby release detection circuit, 14 is a play flag, 1
5 to 18 (- each represents an AND circuit.

In normal processing mode, the graphical output of flag 10 emits a logic rlJ, and the graphical output of flag 11 emits a logic "0".
As a result, the play flag 14 outputs a logic "1", and the AND circuit 18 becomes a logic "1", keeping the standby control unit 12 in an inactive state.

In this state, when flag 10 is set based on the standby 1 command, the 1 output of flag 10 activates standby control unit 12, which is a logic [0]. At this time, the illustrated output of the flag 11 remains at logic "0" and the standby control unit 12 does not generate the illustrated "oscillation control" signal. When the standby control unit (standby control unit) 12 becomes active,
The "clock control" signal shown in the figure is issued, and the branching function by the outer circuit 2 is stopped.

When a release input is applied to release the first standby mode, the standby release detection circuit 13 detects this and controls the flags 10 and 11 to be reset. At this time, the flag 11 is not affected at all since it is originally in a reset state, but the flag 10 is reset. At this time, since the oscillation circuit 1 was in oscillation operation, the play flag 14 continued to generate the logic rlJ, and the AND circuit 18 issued the logic rlJ, and the standby control unit) l 2id inactive 11;9
Returned to M. Hochi, juice from dividing circuit 2! The security function will be restored.

Under normal processing mode, when flag 11 is set based on the standby 2 instruction, the illustrated output of flag 11 is logic ill. As a result, the play flag 14 emits a logic "0", the AND circuit 18 becomes a logic "0",
The standby control unit 12 enters the active state. At this time, the standby control unit 12, where the indicated output of the flag 11 is logic "1", also outputs the indicated "oscillation control" signal. As a result, the oscillation circuit 1 is stopped and the outer circuit 2 is also stopped.

When a release input is given to release the second standby mode, the standby release detection circuit 13 detects this and controls the flags 10 and [1 to be reset, respectively. At this time, the flag 10 is Since it is originally in a reset state, it does not receive any shadow 1. When flag 11 is reset, the illustrated output of flag 11 is a logic "0". As a result, the standby control cost unit 12 (indicated by □) and the AND circuit 18 is still
The figure shows that it is at the exact size of J [Oscillation control]
Drop only the signal. The oscillation circuit 1 thereby resumes its oscillation operation, and the timer/counter 4 temporarily counts the output from the oscillation circuit 1. When the timer/counter 4 issues a carry output, the play flag 14 issues a logic rlJ (because the illustrated outputs of the flag 11 are already s and rOJ), and the AND circuit 18 outputs a logic "rlJ".
1” is emitted.

Then, the standby control unit 12 is deactivated. )211, drop the [clock control] signal and enter the 1st prisoner processing mode.

(Regulation) As described in detail, according to the present invention, the first standby
mode and the second standby mode can each be selectively generated by a command. Particularly in the second standby mode, it is possible to disable the clock generation function in the oscillation circuit 1 and create a low power consumption f line. However, when canceling the second standby mode, it is necessary to wait until the operation of the optical oscillator circuit becomes stable. In the case of the illustrated example, a program counter is used as the timer that provides the wait, and the only thing newly installed on one chip is the standby control and OJ path. It will be enough.

[Brief explanation of drawings]

FIG. 1 is a configuration of a one-chip microcomputer to which the present invention is applied, FIG. 2 is an explanatory diagram illustrating one embodiment of control regarding the first standby mode, and FIG.
An embodiment of Time Nayat in standby mode of
FIG. 4 is an explanatory diagram illustrating one embodiment of control related to the second standby mode, FIG. 5 is a time chart of one embodiment during the second standby mode, and FIG. 6 shows the occurrence of standby mode. FIG. 11 shows a main part configuration of an embodiment of a part related to and cancellation. During tuning, l is the Q swing circuit, 2 is the outer circuit, 3 is the center circuit, 4 is the timer/counter, and 5 is)? , AM, 5 is H, O
M, 7 is an input/output circuit section, 8 is a standby control circuit, It) U standby l flag, 1 ] +
i x Tanhigh 2 flag, 12 represents the standby control unit. Patent applicant Fujitsu Limited

Claims (2)

[Claims] (1) A microcomputer that includes at least an oscillation circuit and a processing section including an arithmetic processing circuit,
The program counter in the processing unit holds the address of the next instruction to be executed, the operation of the processing unit is stopped with each register holding information, and the excavation circuit clocks the processing unit while it is operating. A standby mode in which a first standby mode in which the signal supply is stopped and a second standby mode in which the operation of the former processing unit is stopped and the oscillation operation of the excavation circuit is also caused by a block command is generated. control circuit,
a standby release circuit that detects a standby release signal and starts supplying the clock signal or activates the oscillation circuit and releases the processing section from a stopped state in response to the first and second standby modes; A microcomputer with a built-in standby function. (2) The standby function according to claim (1), wherein in the second standby mode, the stopped state of the processing section is canceled after a predetermined period of time has elapsed from activation of the oscillation circuit. Built-in microcomputer.