JPS58205210A - Controller - Google Patents

Controller

Info

Publication number
JPS58205210A
JPS58205210A JP57087867A JP8786782A JPS58205210A JP S58205210 A JPS58205210 A JP S58205210A JP 57087867 A JP57087867 A JP 57087867A JP 8786782 A JP8786782 A JP 8786782A JP S58205210 A JPS58205210 A JP S58205210A
Authority
JP
Japan
Prior art keywords
signal
output
load
test
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57087867A
Other languages
Japanese (ja)
Inventor
Kazuo Nakajima
一男 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57087867A priority Critical patent/JPS58205210A/en
Publication of JPS58205210A publication Critical patent/JPS58205210A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00Testing or monitoring of control systems or parts thereof
    • G05B23/02Electric testing or monitoring
    • G05B23/0205Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
    • G05B23/0218Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
    • G05B23/0256Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults injecting test signals and analyzing monitored process response, e.g. injecting the test signal while interrupting the normal operation of the monitored system; superimposing the test signal onto a control signal during normal operation of the monitored system

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Abstract

PURPOSE:To find faults on an output converter and a load side in their early stages and to prevent abnormal operation by outputting the drive testing signal and actual driving signal of a load alternately and cyclically, and comparing the testing signal and response signal of the load with each other. CONSTITUTION:A control computing element 2 receives input signals b1-b3 from input converters 1 all the time to perform control operations and supplies output signals c1-c3 to output signal switches 5. The switches 5 receive the output signals c1-c3, and test mode signals e1-e3, test signals f1-f3, and output and test mode signals e1-e3, test signals f1-f3, and output gate signal g1-g3 from a test signal generator and comparator 7 to switch the output signals c1- c3 and test signals f1-f3, obtaining output signals h1-h3. Those output signals h1-h3 are converted by output converters 3 into load signals d1-d3, which are inputted to load signal detectors 6 to be fed back to the test signal generator and comparator 7 as response signals j1-j3. The comparator compares test signals e' with the response signals j1-j3 to output comparison result output gate signals g1-g3 to the output signal switches 5.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、プラントデータを入力し、人力データに従っ
て演算処理をし演刃。結果に従って出力信号を発生12
、負荷の駆#Iを行なう制御装置に四するっ 発明の技術的背景とそのrHf5 A点従来の制御装置
について職1図を基に説明する、第11・Aに示すもの
は入力信号が3種、出力信号が3f1!!の壜台のもの
である、従来制御装置は、プラントからの人力信号a−
a (a+ 、at 、as )を人力変換器1を介I
−制御演算器2で処理可能々デーN(い (−=f(fl(bI 、b2 、bl )、f2 (
bI 、b2 、bs )fs (bI 、 bz 、
 bl))−)なる演算を制御演算器2で実行し、出力
信号c=c(cI+c2 、cg )(cl =fl(
bI 、bt +b! ’) +c2 =f2 (bI
 1 b21 bl ) +cS −=fN(bl、b
2.b、)をη:出した後、出力変換器3を介し負荷4
の駆動を・行なっている。この様な方式であると制@装
置により負荷が正常に駆動されているか否かは、制@装
置への負荷を駆動する入力条件が5見立し、実際に負荷
駆動の出力信号が発生した時点でのみ検出されるうこの
時は、負荷の誤動作、誤不動作によりプラント運転に支
障をきたしている場合が多く、プラントの稼動率の11
(下の大きな原因の一つと1っている。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention inputs plant data and performs arithmetic processing according to human data. Generate output signal according to result12
, Technical background of the invention and its rHf5 Point A The conventional control device will be explained based on Figure 1. Seed, output signal is 3f1! ! The conventional control device, which is for the bottle stand of
a (a+, at, as) through human power converter 1
- Data N(i(-=f(fl(bI, b2, bl), f2(bI, b2, bl), f2(
bI , b2 , bs ) fs (bI , bz ,
bl))-) is executed by the control calculator 2, and the output signal c=c(cI+c2,cg)(cl=fl(
bI, bt +b! ') +c2 = f2 (bI
1 b21 bl ) +cS −=fN(bl, b
2. After outputting η: b,), the load 4 is passed through the output converter 3
It is driving the In this type of system, whether or not the load is being driven normally by the control device is based on the following five conditions: In many cases, this is detected only at the point in time when the plant operation is hindered due to malfunction or malfunction of the load, and the plant's operating rate decreases to 11%.
(This is considered one of the major causes below.

発明の目的 本発明は負荷の駆動テスト信号全常時サイクリックに出
力し7、テスト信号に対する負荷信号を応′J:r信号
としてフィードバンク(7、テストfFT 号ト応答信
号とを比較し、比較結果腎常箇所のロケーション表示を
行なうとともに、負荷が異常動作をしない様出力信号を
常時OFFとさせることにより、出力変換器及び負荷側
の異常の早期発見及び&Mの異常動作の防止が可能とな
り、プラント稼動、もの大巾向上が可能な制@装胃を提
供するものであるう 発明の概要 本発明は複数の入力信号を入力変換器を介しr受け、人
力信号街基に、制御演W器で予じめ定められた制御演算
を実施し、9荷の駆動を行々う、′Nに出力変換器13
)を介17出力信号を出力する制机内iにおいて、テス
ト(言舛、テストモード1言号を発生し、出力信号切替
器に出力すると共に、テスト信号と、@荷信号検出器か
らの応答1言号とを田・ヒし、比較結果出力ゲー ト信
号を出力信号切替器Cτ出力するとともに7オルトロ一
ケー/ヨン表示を行斤うテスト信号発生/比$器と、テ
スト信号発生/ tt ff 6からのテスBir号と
、テストモード信号とを受け、負荷の実駆動13号、テ
ストf言号の切替えを行々う出力信号切替器F器と負荷
の動作信号を噴出1−1応答信号と【−でテスト信号発
生/比較器へ出力fる負荷信号検出器とを設け、負荷の
駆動テスト信号を負荷の実駆動信号と交互に常時サイク
リックに出力し、テスト信号に対する負荷の応答慮号と
を比較し比較結果外宮箇所のロケーション表示全行なう
とともに負荷が異常動作しhいよう出力信号を常時OF
F’とさせることを特徴とし、出力室415及び、負荷
側の異常の早期発見と、負荷の異常動作の防止が可能な
制御装置であるう発明の実施例 本発明の構成を第2図全用いて説明する2、この−実7
1!!i引1で?i説明全簡便にする為、入力信号を3
挿、出力信−号を3種、−出力信−号に対し負荷が一!
1一番で接続されているものとする。
OBJECTS OF THE INVENTION The present invention constantly cyclically outputs a load drive test signal 7, and compares the load signal with the test fFT response signal as a response signal to a feed bank (7). As a result, by displaying the location of the kidney abnormality and keeping the output signal OFF at all times to prevent the load from operating abnormally, it is possible to early detect abnormalities on the output converter and load side, and prevent abnormal operation of the &M. SUMMARY OF THE INVENTION The present invention provides a control system that can significantly improve plant operation.The present invention provides a control system that can receive a plurality of input signals through an input converter, and convert it into a human-powered signal station and a control operator. A predetermined control calculation is performed at 'N to drive the nine loads.
) in the controller i that outputs the 17 output signal, generates a test (in other words, test mode 1 word) and outputs it to the output signal switcher, and also outputs the test signal and the response from the load signal detector. A test signal generator/ratio device which outputs a comparison result output gate signal to an output signal switcher Cτ and displays a 7 orthogonal key/yon, and a test signal generator/tt. Receives the test Bir number from ff 6 and the test mode signal, and outputs the output signal switch F unit that switches between the actual drive number 13 of the load and the test f word, and outputs the load operation signal 1-1 response A load signal detector that generates a test signal/outputs it to a comparator at [-] is provided, and the load drive test signal is always cyclically output alternately with the load actual drive signal to detect the load response to the test signal. The location of the outer shrine is displayed as a result of the comparison, and the output signal is always turned off to prevent the load from operating abnormally.
Embodiment of the present invention The configuration of the present invention is shown in FIG. 2, this-actual 7
1! ! With i pull 1? iTo simplify the explanation, input signals are 3
Insertion, three types of output signals, one load for each output signal!
1. It is assumed that the connection is made at number 1.

本発明のit;II イ、司装置は、プラントからの人
力信号π:a(al、a2.a3)を受け、制御演算器
#2でケ(理可能なは号b ”’ b (”+ + b
2 + ”3 )に変換する人力変換器1と、人力変換
器1から出力さfl、る人力18号b=b(b、 、b
2.h、 )を受け、予じめ定められた制御演算を実施
し、出力信号τ=c(cl。
The controller of the present invention receives the human power signal π:a(al, a2.a3) from the plant, and uses the control calculator #2 to calculate the number b ``' b (''+ +b
2 + "3)", human power converter 1 outputs fl, human power No. 18 b = b (b, , b
2. h, ), a predetermined control calculation is performed, and the output signal τ=c(cl.

C!ICりを出力する制御演′W、器2と、制御演算?
52からの出力信号下と、テスト信号発生/比較器7か
らのテストモード信号e=e(e) 、e2+e3 )
丁 とテスト信号付=t (t H+ t211R)と出力
ゲー(信号FZ”’g($1’+ + g2+ gq 
)を受け、出ノフ信@dとテ壓 スト信号糾とを切替え、出力信号h=h (h、、 、
 b2゜b3)を出力する出力信叶ζjl替器5と、出
力信号上1替器5がらの出力信号h=h(hl、b2 
、b3 ’)を予は負荷信号d=d(d+ 、d? 、
ds )に変換する出力ti命令器と、負荷fr4+t
 d 14出り、応81% 号+=+ (+、 。
C! Control operation W, device 2, and control operation that outputs IC signal?
52 and the test mode signal e=e(e), e2+e3) from the test signal generator/comparator 7.
With test signal = t (t H+ t211R) and output game (signal FZ'''g ($1'+ + g2+ gq
), the output signal @d and the test signal are switched, and the output signal h=h (h, , ,
b2゜b3), and output signal h=h(hl, b2
, b3') is the load signal d=d(d+, d?,
ds) and the load fr4+t
d 14 out, 81% issue +=+ (+, .

Jz+Jt)としてテスト信号発生/比較67 ttて
出1]する負?rr信号検出器6と11ζ’l門袈得の
操作端でもる長 − 負荷4と、テストは+>n、“ノーストモード信号eを
発生1.出力信号切替器5に出ノJするととも(lこ、
テスト信号夏と負荷信号検出器6からの応答信目jとを
L+」りし、比較器・匙出力)′−ト1言号iをl−j
 、り信号切替器5に出力するとともに、フォルト「コ
ケーンヨン表示f行なうテスト信号発生/比較器とから
構成される。
Generate/compare test signal as Jz+Jt) 67 tt and output 1] Negative? rr signal detector 6 and 11ζ'l at the operating end of the gate - load 4, test +>n, "no-stop mode signal e is generated 1. When output signal switch 5 is output ( l-ko,
The test signal summer and the response signal j from the load signal detector 6 are L+', and the comparator/spoon output)'-to1 word i is l-j.
, and a test signal generator/comparator that outputs the signal to the signal switch 5 and also indicates a fault.

本窒明の作用を第2図、第3図、肥4 ii2+ 、第
5図、第6図を用イテ説明−J−2)、制御11!涜1
’[i52 h、常時人刃傷:換器lを介し人力される
人力信号すをtg号切牲器5Vc出力する。テストアイ
デント/モード発生部72は回路1〜3の順にテストア
イデントを作成−シ、先ずn=n(0,0)、(n+ 
=Q、11゜=n )、p=p(o、o)、(p+ =
O,l)鵞=O)をテストモード出力部75、テスト信
号出方部76、テスト異常表示部77、出カゲート濡号
出カ部78、応答信号選択部71に出方する。テストモ
ード出力部75Vi信号rt=n(n、n)fcj リ
fス)モー )”信号e=e(1,0,O)、 (e+
 ==l +e2 ==Q、63=Q)を1B力するっ
又テスト1g号出力部76けテスト信壓 号n=f (1,0,0)、 (fl =1 、 h 
=Q、 fs =O)及びテスト信長Q=(f) 、 
ft 、 +31”=ft t 出力tZ・っここでN
+ 、h +f31五はiによりfI+f2+貫3 の
いずれかを選択すふものであるうテスト信号qばし/フ
ァし・ラス信号記+?部73に記憶されるう又出力ゲー
トIS号出力部78け現状異常熱[7を仮定]2、g=
12(1,1,1)を11−1カする。出カ信号切10
(第3図参照)は、信号e =e (1+ 0 、Q 
) +否 付=f(1,0,0)12=g(1,1,1)とから出
力有信号c2.c3が出力されるっテスト信・号el 
(=h+)は出力変換器3を介し、負荷信号d、を発生
させる、9荷信号検出器6(第4図参照)は負荷信号検
出部61で負荷信号d1を検出し、信号変換部62によ
り信号変換を行ない、応答信号J””J (J+ 、 
+7 。
The action of this nitrogen light is explained using Fig. 2, Fig. 3, Fig. 4 ii2+, Fig. 5, and Fig. 6-J-2), Control 11! Blasphemy 1
'[i52 h, Constant human knife injury: A human power signal is outputted to the TG cutter 5Vc via the converter L. The test ident/mode generator 72 generates test idents in the order of circuits 1 to 3. First, n=n(0,0), (n+
=Q, 11°=n), p=p(o,o), (p+ =
O, l) = O) is output to the test mode output section 75, the test signal output section 76, the test abnormality display section 77, the output gate signal output section 78, and the response signal selection section 71. Test mode output section 75Vi signal rt=n(n,n)fcj
==l +e2 ==Q, 63=Q) is output by 1B, and test signal 1g output section 76 test signal signal n=f (1,0,0), (fl =1, h
= Q, fs = O) and test Nobunaga Q = (f),
ft, +31”=ft t Output tZ・k Here N
+ , h + f315 is a test signal that selects either fI + f2 + 3 depending on i. Output gate IS number stored in unit 73 Output unit 78 Current abnormal heat [assuming 7] 2, g=
Multiply 12 (1, 1, 1) by 11-1. Output signal off 10
(See Figure 3) is the signal e = e (1+ 0, Q
)+Negation=f(1,0,0)12=g(1,1,1), output presence signal c2. c3 is output test signal/signal el
(=h+) generates a load signal d through the output converter 3.The load signal detector 6 (see FIG. 4) detects the load signal d1 in the load signal detector 61, and the signal converter 62 The response signal J""J (J+,
+7.

」3)を出力する。、’J2 、js lけc2.c3
に対応した応答信号、LFiテスト信号e!に対応した
応答信号)信号Jは応答信号選択部71に入力される、
応答信号選択部71は、前記信号rl=p(n 、 +
1 ’)vでより、応答信号ハを選択1.1とする。、
(1−(J+ 。
”3) is output. ,'J2,js lketc2. c3
Response signal corresponding to LFi test signal e! (response signal corresponding to) signal J is input to the response signal selection section 71,
The response signal selection unit 71 selects the signal rl=p(n , +
1') Based on v, the response signal C is selected as 1.1. ,
(1-(J+.

jz 、+3)p(0,0)=j+ )応答信号/レフ
ァレンス信号比較部74は、前記信号1(=3+)とレ
ファレンス信号記憶部73で記憶しているテスト信号I
t(=1)と比較をL、比較結果を比較エラー信号mと
してテストアイデント/モード発生部72及び、出力ゲ
ート出力部78に出力するっ(比較エラー有でm−1,
無しでm = Q ) m = 1のときは%  ’?
=e(1,0,0)について同様なテストを規定回数(
例えば5回)行なう。比較エラーが規定回数(例えば3
回)以上であれば回路異常とみなされ、出カデート信号
出カ部78け12g(0,l、1)を出方信号切替器5
に出方し、hlを常時IO”にする。又テスト異常表示
部は回路1に対応するエラー表示器を点灯するっ 比較エラーがない場合或はエラー表示を行なった贅、テ
ストアイデント/モード発生部72け、回路2をチェッ
クする為Kをn(0,0)がらn(1゜0 ) トLn
=n(1+o)+”’I ==l 、n2 =O) +
 p=p(1,0) 、 (pI=1 、r)t =O
)ラチストモ−ト信号出力部75、テスト信号出刃部7
6、テスト異常表示部77、出カゲート信丹出カ部78
及び、応4信号直択部71に出力し、回路lと同様なチ
ェックを実楕し、比較エラー無し又比較エラーが規宇回
番N内であれば、冗=q(fl、1.1)、比較エラー
が纜定回数以上であればFl’=g(0、0、1)とし
、回路3のチェッチに移ろうテストアイデント/モード
発生部72けπ=n(0,1)、p=p(’0.1)を
出力し、回路3のチェックを実施する。回路3のチェッ
クが終了すると回路1のチェックに戻る。
jz , +3)p(0,0)=j+) The response signal/reference signal comparison section 74 compares the signal 1 (=3+) with the test signal I stored in the reference signal storage section 73.
t (=1) and the comparison is L, and the comparison result is output as a comparison error signal m to the test ident/mode generation section 72 and the output gate output section 78 (m-1 if there is a comparison error,
Without m = Q) When m = 1, %'?
= e (1, 0, 0) similar test is performed a specified number of times (
For example, 5 times). If the comparison error occurs a specified number of times (e.g. 3
times) or more, it is considered a circuit abnormality, and the output signal switch 5
The test error display section lights up the error display corresponding to circuit 1. If there is no error or an error display is performed, the test ID/mode is displayed. To check the circuit 2 in the generating section 72, set K from n(0,0) to n(1°0) Ln
=n(1+o)+”'I ==l, n2 =O) +
p=p(1,0), (pI=1,r)t=O
) Lattist mote signal output section 75, test signal output section 7
6. Test abnormality display section 77, output gate Shintan output section 78
Then, it is output to the response 4 signal direct selection unit 71, and the same check as in circuit 1 is performed. ), if the comparison error exceeds a certain number of times, set Fl' = g (0, 0, 1) and move on to checking circuit 3. Test identity/mode generator 72 π = n (0, 1), Output p=p('0.1) and check circuit 3. When the check of circuit 3 is completed, the process returns to the check of circuit 1.

以上の如く回路1〜3を順次サイクリックにチェックす
る(第6図)っ 第6図中、■は実駆動信号出力部、n +a yスト信
号出力部の動作を示t。以りにより、出力変換器3から
負荷の動作まで・全体を通したチェックと異常箇所の明
確化が可能とkった、 発明の効果 本発明の説明では、出力Q3.!i(3回路)として説
明したが、31(3何路)と限定1−る必要け々い、説
明では、出力信号Cと負荷4が1711に接続さ1tて
いると仮定し、tが、必ず1.7もその必要はなく、第
71Aのlノ[1く、制御演算器2から+r、)J(信
号が1α列信号の形態で出力さfl、ている場合も適1
1出来ることはいうまでもないっ又竺8図の如く出力変
換器3と負荷との中離が遠く制御1寅算門2からの並列
に出力される馬力信号をマルチ、)し・クスし、出力変
換器3の間を多重伝・丙j−でいる場合も適用出来るこ
とはいうまでもない、 又、複数の出力回路をブ1コックに寸とに’> (、ブ
ロック毎にアドレスを予じめ定めておき、アドレスを指
定することにより、ブロック単位のテストパターン信号
を発生させ、テストが実施可能であることはいうまで本
ないう又制御装置が計算機を用いたシステム成はディジ
タル回路或はリレーシーケンスによって構成されていて
も全て適用可能であるう以上により、プラント制御装置
の出力変換器及び負荷側の異常の早期発見及び負荷の異
常動作の防止が可能で、プラント稼動率の大向上を可能
とする制御装置の提供が回部となったっ
As described above, the circuits 1 to 3 are sequentially and cyclically checked (FIG. 6). In FIG. As a result, it is possible to check the entire operation from the output converter 3 to the operation of the load, and to clarify abnormalities.Advantages of the Invention In the description of the present invention, the output Q3. ! i (3 circuits), but it is necessary to limit it to 31 (3 circuits). In the explanation, it is assumed that the output signal C and the load 4 are connected to 1711, and t is It is not necessary to use 1.7, and it is also suitable if the 71A signal is output in the form of a 1α column signal.
1 It goes without saying that it is possible to do this by multiplying the horsepower signals output in parallel from control 1 and control gate 2 so that the output converter 3 and the load are far apart, as shown in Figure 8. , it goes without saying that it can be applied to the case where there is multiple transmission between the output converters 3. Also, it can be applied to multiple output circuits in one block. It goes without saying that tests can be performed by generating test pattern signals in block units by predetermining addresses and specifying addresses. Or, even if it is configured by a relay sequence, it can be applied to all systems.The above enables early detection of abnormalities on the output converter and load side of the plant control device, prevents abnormal load operation, and greatly increases the plant operating rate. Our goal is to provide control devices that enable improvements.

【図面の簡単な説明】[Brief explanation of drawings]

第11ゾは従来の制御1装置を示すブロック図、第2図
は本発明の制御装置を示すブロック図、第3図け1((
力信号切替器を示す11]]烙図、第4図は負荷信号検
出器を示すブロック1図、第5図はテスト信号発生/比
較器を示tブロック図、第6図は負荷実嘱動及4.gテ
スト信号出力との関係を示すタイムチャート、第7図は
制御演轡器からの出力信号Cが5判信号の場合の本発明
の構成を示すブロック図、第8図は制御演算器と出力変
換器間を多重伝送している場合の本発明の構成を示すブ
ロック図である。 1−=−1入力変換器   2・・・lll ?’9J
演′W、器3・・・・・出力変換器    4・・・・
負 荷5・・・・・出力信号切鉾器  6・・・負荷1
に月=9y出器7991.テスト1バ号発生/比較器 B 、、、、、  )ランスミック(直列信−号)9・
・・・・Vン−ハ(1’11信号)10・・・・・デマ
ルチブレフサ 11・・・・・マルチプレクサ
Figure 11 is a block diagram showing a conventional control device, Figure 2 is a block diagram showing a control device of the present invention, and Figure 3 is a block diagram showing a conventional control device.
Figure 4 is a block diagram showing the load signal detector, Figure 5 is a block diagram showing the test signal generator/comparator, and Figure 6 is a block diagram showing the load signal switch. and 4. 7 is a block diagram showing the configuration of the present invention when the output signal C from the control calculator is a 5 format signal, and FIG. 8 is a diagram showing the control calculator and output. FIG. 2 is a block diagram showing the configuration of the present invention when multiplex transmission is performed between converters. 1-=-1 input converter 2...llll? '9J
Performance'W, device 3... Output converter 4...
Load 5...Output signal cutter 6...Load 1
Month = 9y output device 7991. Test 1 signal generation/comparator B , , , ) transmic (serial signal) 9.
...Vn-ha (1'11 signal) 10...Demultiplexer 11...Multiplexer

Claims (1)

【特許請求の範囲】[Claims] 複数の入力信号を入力変換器を介して受け、入力信号を
某圧制御演算器予じめ定められた制御演算を実施1−1
負荷の駆動を行なう為に出力変換器ヰを介し出力信号を
出力する制御装置において、テスト信号、テストモード
信号を発生し、出力信号切替器に出力すると共番て、テ
スト信号と、負荷信号検出器からの応答信号とを比較し
、比較結果出力グー ←信号を出力信号切替器に出力す
ると共に、フォルトローケージ32表示を行がうテスト
信号発生/比較器と、テスト信号を生/比較器≠がらの
テスト信号と、テストモード信号とを受は負荷の実駆動
信号、テスh (g号の切替えを行なう出力信号切替器
と、負荷の動作信−号を検出12、応答信号とl−でテ
スト信号発生/比較器へ出力する負荷信号検出器とを設
け、負荷の駆動テスト信号を負荷の実駆動信号と交互に
常時サイクリックに出力1〜、テスト信号に対する負荷
の応′$r信号とを比較し比較結果異常箇所のロケーシ
ョン表示をで1なうと共に、負荷が異常動作しkい種出
力信号を常時OFFとさせることを特徴とし、出力変換
器及び、負荷側の異常の早期発見上、負荷の異常動作の
防止が可能な制御装置間。
Receive a plurality of input signals via an input converter, and perform predetermined control calculations on the input signals to a certain pressure control calculator 1-1
In a control device that outputs an output signal via an output converter in order to drive a load, when a test signal and a test mode signal are generated and output to an output signal switcher, the test signal and load signal are detected. ← A test signal generator/comparator that outputs the signal to the output signal switch and displays the fault low cage 32, and a test signal generator/comparator that outputs the signal to the output signal switch and displays the fault ≠Receives the empty test signal and the test mode signal, and outputs the actual drive signal of the load, the output signal switcher that switches the test h (g), detects the load operating signal 12, and outputs the response signal and l- A test signal generator/load signal detector for outputting to the comparator is provided, and the load drive test signal is always cyclically outputted alternately with the load actual drive signal, and the load response '$r signal to the test signal is It is characterized by displaying the location of the abnormality point as a result of the comparison, and also by constantly turning off the output signal of the type where the load operates abnormally, which enables early detection of abnormalities on the output converter and the load side. Above, between control devices that can prevent abnormal load operation.
JP57087867A 1982-05-26 1982-05-26 Controller Pending JPS58205210A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57087867A JPS58205210A (en) 1982-05-26 1982-05-26 Controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57087867A JPS58205210A (en) 1982-05-26 1982-05-26 Controller

Publications (1)

Publication Number Publication Date
JPS58205210A true JPS58205210A (en) 1983-11-30

Family

ID=13926821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57087867A Pending JPS58205210A (en) 1982-05-26 1982-05-26 Controller

Country Status (1)

Country Link
JP (1) JPS58205210A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0697637A1 (en) * 1994-08-17 1996-02-21 G. Kromschröder Aktiengesellschaft Method for monitoring the functioning of a controlling and regulating system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0697637A1 (en) * 1994-08-17 1996-02-21 G. Kromschröder Aktiengesellschaft Method for monitoring the functioning of a controlling and regulating system

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