JPS582757A - Detecting device for trouble of signal transmission line - Google Patents

Abstract

PURPOSE:To detect troubles easily in a short time, by converting signals, which are transmitted through plural signal transmission lines, to serial signals in the transmission side and the receiving side and discriminating a trouble on a basis of the number of times of uncoincidence between them. CONSTITUTION:A parallel test signal is generated in a signal generating circuit 3 and is supplied to signal transmission lines 21-2L. Parallel signals given to signal transmission lines 21-2L are converted to serial signals, which are arranged in the order of signal transmission lines 21-2L, in two converting circuits 4 and 4'. The output of the converting circuit is given directly to a discriminating circuit 6, and the output of the converting circuit 4' is given to the discriminating circuit 6 through an echo signal transmission line 5. Outputs of converting circuits 4 and 4' are compared with each other successively in a coincidence detecting circuit of the discriminating circuit 6; and if the uncoincidence is detected repeatedly over the prescribed number of times, it is discriminated that the signal transmission line is faulty.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection device for detecting a failure in a signal transmission line or a signal transmission line connecting a plurality of 4GK panels.

FIG. 1 schematically shows signal transmission lines wired between panels. A signal transmission line 21. between the board 1 and the board 1'.
2t When signal transmission line 9 is shown through 2Lv, if there is a failure in signal transmission line 2, 2□..., 2L,
An abnormality in the operation of the panel was detected when an operation button on the panel malfunctioned, and a failure in the signal transmission line 2 was detected based on this. However, even if it is known that the malfunction of the board is caused by a failure in a signal transmission line, it is not easy to find out which signal transmission line is at fault. In addition, inspection of signal transmission lines must be carried out in a short period of time to prevent a drop in the operating rate of the plant, but this is difficult in large-scale plants with many signal transmission lines.

An object of the present invention is to provide a failure detection device that can easily detect failures in a short time.

FIG. 2 shows an embodiment of the present invention.

In the same figure, 1.1' is a panel such as a control panel 2+ -2m -
..., 2L is L for transmitting signals between panels 1 and 1'
This is the signal transmission line of the book. 3 is provided in one panel 1,
A signal generation circuit 4 that generates a plurality of test signals in parallel is provided in the board 1, a conversion circuit that converts the parallel test signals generated by the signal generation circuit 3 into serial signals, and 4' is @ 1', and the signal generation circuit 3
A parallel test signal generated by the I/F converter circuit 4 is supplied via the signal transmission line 2, and the outputs of the converter circuits 4 and 4, which are conversion circuits that convert the test signal into a serial signal, are connected to the I/R so that they correspond to each other. cfk is on. That is, for example, the parallel signals applied to the signal transmission lines 21 to 2L are transmitted to the signal transmission lines 2.4 in both of the two conversion circuits 4.4'. ~2
It is converted into serial signals arranged in the order of L. Conversion circuit 4
The output of the conversion circuit 4' is directly applied to the determination circuit 6, and the output of the conversion circuit 4' is applied to the determination circuit 6 via the echo signal transmission line 5.

The determination circuit 6 is configured, for example, as shown in FIG. The outputs of the conversion circuits 4 and 4' are sequentially compared by the matching circuit 7. As a result, for each of the test signals generated from the signal generation circuit 3, the signal transmission lines (21 to 2L)
If the result of a 0 comparison in which what is transmitted via the 0 and what is not transmitted is a mismatch, a signal "1" indicating a mismatch is output from the matching circuit 7.

Memory circuits 10 and 10' are connected to signal transmission lines 21 to 2L.
The contents of these addresses AH-'-AL, including addresses A1 to AL corresponding to each of the addresses AH-'-AL, are set to "0" K prior to the start of the determination operation.At first, the selection signal 11 is selected by the memory circuit 10. The zero-power counter circuit 12 to be used for each of the test signals,
In synchronization with the sequential comparison by the matching circuit 7, the Memine circuit 1
0 address (Al to AL) is sequentially specified. The display 13 indicates the specified address, and therefore the signal transmission line V* corresponding to the test signal being compared by the coincidence circuit 7. The counter circuit 12 The specified address (Al
The contents of ~AL) are transferred to the register circuit 14. The 0 addition circuit 8 adds #%' of the V register circuit I4 to the output [lJ or I"OJ of the lk circuit 7. The 0 addition result is transferred to the specified memory 10. is written to the specified address.

The above 15''& operation is repeated a predetermined number of times (M times) for all signal transmission lines. After that, the selection signal 11
'The memory circuit 1σ is selected.

The discrimination circuit 9 determines that the addition result in the addition circuit 8 is a predetermined number a.
(N times) or more, K ro” otherwise, “
The output of the 0 discrimination circuit 9 which outputs ``1'' is sent to the memory circuit 10'.
is written to the specified address. This operation is performed once for all signal transmission lines. The contents written in the memory circuit 10' are stored in the flip-flop circuit 1.
5 and is displayed on the display 13'. Indicator 13'17) The faulty signal transmission line can be identified from the display.

In the above embodiment, multiple test signals transmitted in parallel via the signal transmission line are converted into serial signals and sent back, so only one return line (echo signal transmission line) is required. , the number of return lines can be reduced compared to the case where parallel signals are returned as is. Further, only one matching circuit is required for comparing the returned signals. Therefore, even if the plant is large-scale and has many signal transmission lines, it is possible to reliably detect failures with a device with a simple configuration.In addition, each signal transmission line can be sent a test signal multiple times (M times). It is determined that there is a true failure only when the number of mismatches is 8 or more times. FIG. 4 shows another example of the determination circuit 6. In this example, the memory circuit 1σ of FIG. 3 is omitted, and the output of the memory circuit 10 is transferred to the switching device 16.
The signal is selectively input to the register circuit 14 or the discriminator circuit 9. In the determination circuit 6 of this example, the switching device 16 selects the register circuit 14 while the matching circuit 7 performs the comparison and accumulates the number of mismatches. After the matching circuit 71C performs the comparison M times for each signal transmission line, the switching device 16 selects the discrimination circuit 9, and the accumulated value of the number of mismatches stored in the memory circuit 10 is determined by the discrimination circuit 9 to a predetermined value. A determination is made as to whether or not the number of times N is greater than or equal to N.

In other respects, it is similar to the determination circuit shown in FIG.

FIG. 5 shows a predetermined circuit using a duplex memory circuit 10 of FIG. 4. In FIG. That is, regarding the input signal ←, the outputs of the two memory circuits 10A and IOH, which perform the same processing under the same conditions, are compared in the comparator circuit 17, and if they match, the outputs are sent to the register circuit via the switching device 16. 14 or the discrimination circuit 9. If they do not match, the comparison circuit 17 sets the 7-lip 7 stomach-tub circuit 15.Based on this, the judgment circuit 6
(4IK's memory circuit 10M, 10B, etc.): It is possible to display a failure in a signal transmission line with a simple configuration, quickly and reliably. I can do it〇

[Brief explanation of the drawing]

Figure 1 shows the two boards and these! "f" indicates the signal transmission line connecting
Schematic diagram, FIG. 2 is a schematic wiring diagram showing one embodiment of the present invention,
3 to 5 are block diagrams showing examples of the determination circuit of FIG. 2.

Claims (1)

[Claims] a signal generation circuit that generates a plurality of test signals in parallel; and a first conversion circuit that transmits the test signals through a plurality of signal transmission lines to be tested and converts the test signals into serial signals. The test signal is transmitted through the signal transmission line, and the test signal is transmitted to the first conversion circuit and the corresponding output signal of the second conversion circuit is transmitted to the first conversion circuit. The signal transmission line is repeatedly compared a predetermined number of times, and when the two signals being compared do not match for each of the signal transmission lines repeatedly for a second predetermined number of times or more, there is a failure in the signal transmission line. A signal transmission line failure detection device comprising a determination circuit for determining.