JPS58203698A - Semiconductor memory having auxiliary line - Google Patents

Abstract

PURPOSE:To obtain a memory having a defects relief circuit, by arranging n/2 lines of normal bit lines of an arranged memory array, when arranging (n) lines of auxiliary lines, in order to eliminate the unbalance between the memory arrays. CONSTITUTION:The point which differs from a conventional one is that n/2 of the normal bits of memory arrays 16c and 16d are transferred to a part 1 indicated in a memory array 5. Due to this constitution, the length of lead wire 3 can be made to be the same to reduce bad influence given to memory characteristics. In this example, a memory having a stabilized defects relief circuit and giving no bad influence on memory characteristics is realized without increasing the size of a tip. Further, if part of the normal data lines is transferred to other arrays, it does not effect on an auxiliary line controlling circuit. The transfer of the normal data lines is performed including a decoder. The bad influence of the transfer is never caused. The increase of word line length per array due to the addition of (n) lines of auxiliary lines becomes n/2 of data lines so that time delay is lessened in comparison with a conventional method which increases the line by (n) lines.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory equipped with defect relief means,
In particular, the present invention relates to a suitable spare line arrangement and memory array configuration that does not adversely affect memory characteristics.

FIG. 1 shows an example of a block section of a semiconductor memory composed of four memory arrays. 10 is an address buffer, 12a, and 14a is a circuit block including a 2biJY decoder and a common I10 circuit.

14b is a circuit block including an X decoder and a word driver; 16a, 16b, 16c, 16clB memory array; 18r; I sense amplifier; 20 is an I10 control circuit;
2 represents a pit samurai, and 3 represents a word line. When arranging n spare lines 1 and a spare Tecoder in such a semiconductor memory, the spare lines must be placed either above or below the memory array due to the complexity of wiring to the spare lines, chip size, etc. 10,000 memory arrays 15a, 16b, 16c must be arranged together.

The length of the word line 3 between 16d changes, and in memory array (1, 01, (1, 1), the word line length is equal to the spare line, and from memory array (0, O), (0°1). This is undesirable because it causes differences in memory characteristics between the divided arrays, such as an increase in delay time.

It is an object of the present invention to eliminate the imbalance between the memory arrays, and to improve the arrangement of spare lines in a semiconductor memory, which has a stability tube and a defect relief circuit that does not adversely affect memory characteristics. , Memo 1 Noah 1 No configuration is to be proposed '1M.

In order to prevent imbalance between memory arrays, when n spare lines are arranged, n 72 regular bit lines of the arranged memory array may be arranged in other memory arrays. In addition, if the memory array is divided into two with a decoder and a driver in between, and the number of divisions is t, it is clear that - the bit divisor of the moving positive return described above should be set to n/L. be.

Defect relief technology is to provide spare bits in advance in addition to the regular memory bits in the chip, and use the defective bits as spare bits in the ROM (Read-QnLy -
This is a technique for switching using means such as ``Memory''. Generally, only a few spare lines are required. The arrangement of the spare lines and the structure of the memory array will be described below as an embodiment of the present invention.

FIG. 2 shows an embodiment in which the present invention is implemented in a semiconductor memory composed of four memory arrays.

The reference numerals in the figure indicate the same items as those described in FIG. Has1 figure! ! t'naruno (7, memory array 16C216
This is to transfer the positive return pitch H1jln/2 of d to the portion 1 shown in the memory array 5. By using this type of ah, the length of the lead trace 13 can be made the same as Sl, and the influence on the memory characteristics can be reduced @yI1. can.

According to this example, without increasing the size,
It is possible to realize a half-λ, cape-shaped memory that does not affect memory equality, operates stably, and has a defect relief circuit. It is also clear that moving some of the regular data lines to another array has no effect on the spare line control circuit -\.

Furthermore, the well-known data line movement can be carried out including the decoder, and this movement causes no ill effects I#. Furthermore, according to the present invention, prediction! The increase in word line length per l array due to the addition of in lines is equivalent to data #n/2 lines, which reduces delay time and shortens access time compared to an increase of n data lines in the conventional method. Become.

In the above description, the spare data line was used as an example and the array was divided into two. The same applies to the spare word line, so a detailed explanation will be omitted. In addition, in the case of 2 divisions or more, 1 division, n / 1 for each divided array of the above-mentioned normal data line movement.
It is obvious that one book at a time would be better.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the arrangement of spare lines in a conventional semiconductor memory having a four-memory array configuration, and FIG. 2 is a block diagram showing the implementation of the present invention. 1... Reserve line, 2... Bit line, 3... Lead wire, 4... Reserve line decoder, 16a, 16b, 16c
. 16d...Memory array. Agent: Patent Attorney Toshiyuki Usuda - 6-cho Kashu 1 Figure 2

Claims (1)

[Claims] 1. It has a memory array configuration in which two or more word lines or data lines can be divided into individual parts, such as a decoder, and n
In a semiconductor memory having a regular word line or data line in one of the divided memory arrays, n/ of the regular word line or data line in one divided memory array having the reserved line is A semiconductor memory having a reserve line, characterized in that books are transferred to other memory arrays, and the total number of word lines or data lines including reserve iI# of each memory array is made the same.