JPS5820065B2 - Parc Memorino Multicol Seigiyohoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multicall control method for bulk memory whose access is controlled by a plurality of active modules.

Conventionally, magnetic drum storage devices, magnetic disk storage devices, magnetic tape storage devices, etc. have been used as bulk memory in information processing systems. There is a so-called multi-call system that can be used with modules.

However, when a multi-call system is configured using the above storage device as a bulk memory, the following problems occur.

That is, the first active module, e.g.
While the PU (Central Processing Unit) is transferring a data block to/from the bulk memory, if another second CPU requests access to that memory, the acceptance will be delayed until the transfer of the data block is completed. , so while the second
CPU cannot use the above memory.

This causes an inconvenience when it is necessary to immediately transfer data using the memory.

In addition, when the first CPU receives an access request from the second CPU during block transfer between the first CPU and a bulk memory such as a magnetic drum storage device or a magnetic disk storage device, data is exchanged in units of 1 word or 1 byte. There is also a method of distributing the data, but in this case, when looking at the bulk memory from the CPU, data is transferred at a rate of 1 word or 1 byte per rotation of the drum or disk. The characteristics were lost, leading to a deterioration in transfer efficiency.

Furthermore, when a multi-call system such as the one described above is adopted, the program structure becomes much more complex than a hashing single call, and there is a problem in that the software burden is heavy.

This invention was made in view of the above-mentioned circumstances, and uses a high-speed large-capacity static storage device as the bulk memory, and uses only hardware with a simple configuration. Two active modules can be connected by program control similar to single call. It is an object of the present invention to provide a bulk memory multi-call control system that can perform high-speed and efficient data transfer by alternately stealing memory cycles according to the order of reception when an access request is received from a computer.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a multi-call control system circuit according to the present invention, in which reference numeral 11 denotes a first active module (hereinafter referred to as controller A) that uses a static storage device, for example a bulk memory constituted by a core memory. An inverter 12 inverts the bulk memory access request signal (hereinafter always referred to as access request-5) QA sent from the second active module (hereinafter referred to as controller B) that uses the bulk memory. 13 is the inverted access request signal QA.

A flip-flop receives QB and determines the priority according to the acceptance order; 14 is a D-type flip-flop for holding memory cycles that is directly set by the memory start signal MSA of controller A; 15 is a memory start signal MSB of controller B; A D-type flip-flop for holding the memo 1 cycle, 16 an impark for inverting the set output of the flip-flop 13, 17 an inverter for inverting the reset output of the flip-flop 13, 18 19.20 is an impark that inverts the memory cycle end signal EMC of the bulk memory by the static storage device, and 19.20 is a D type for maintaining priority that creates the timing from the access request of each controller A and B to the end of the memory cycle. It's a flip flop.

Therefore, each of the above flip-flops 14, 15, 19,
20 is the die reflex 1~ by the initialization signal INL.
It will be reset.

21 is the set output of the flip-flop 14 and the output of the inverter 18;
Nantes gate for reset control of 20, 22
23 and 24 are Nant gates for resetting the flip-flops 15 and 19 using the set output of the flip-flop 15 and the output of the inverter 18, and 23 and 24 are the access request signals QA when there are access requests from controllers A and B. , Nante gate for returning a disallowance signal to the controller whose memory access request was not accepted when both QBs were 91011, 2
5 receives the set output of the flip-flop 19 and the output of the inverter 16, and together with the Nant gate 23, receives the reception discrimination (permission, disapproval) signal JR1 for the controller A. 26 is a Nant gate of the flip-flop 20. Receiving the set output and the output of the inverter 17, the NAND gate 27 receives the NAND game I.24 and the controller B to obtain the discrimination signal JR2. Nantes gate for direct setting of P20,
28 receives the reset output of the flip-flop 20 and the output of the impark 17 and outputs the flip-flop 1.
This is a Nantes gate for directly setting 9.

The above-mentioned reception discrimination signals JR, , JR2 are also sent to the controllers A and B.

The operation of the device configured in this way will be explained with reference to the time chart shown in FIG.

Here, an access request is first issued from controller A, then an access request is issued from controller B a little later, and then an access request is issued from controller A again before the memory cycle of controller 1 to roller B is completed. will be explained using an example.

First, at the start of operation, the D-type flip-flops 14 and 15 are activated by the initialization signal INL shown in FIG. 2a.
, 19, and 20 are directly reset.

Then, from controller A to 1+0jl shown in Figure 2
When the access request signal QA of the level is issued, and after a short delay, the access request signal QB shown in FIG. 2g is issued from the controller B, the previously issued access request signal Q
A causes the flip-flop 13 to be set.

The set output +T O++ of the flip-flop 13 is inverted by the inverter 16 and supplied to the Nandt gates 25 and 27.

At this time, the flip-flop 19 is in the reset state, so the reset output is as shown in FIG.
+, the output of the Nant gate 27 becomes 11011, which causes the flip-flop 20 to be directly set.

When the access request signal QB is issued from the controller B in this state, the output of the inverter 12 becomes ``1'', but the flip-flop 13 remains set while the access request signal QA from the controller 1 to the roller A is ``0''. is maintained.

Also, at this time, the logic of the Nant gate 24 is established and the output of this gate 1-24 becomes 0'', so that the reception to the controller B is as shown in FIG.
II Q u, and controller B's access request is not accepted at this point.

Therefore, the access request signal QA of controller A becomes °'1.
When ?, the flip-flop 13 enters the reset state, and this reset output ? 10 tt is inverted by the inverter 17 and supplied to the Nandt gate 26°28.

At this time, since the flip-flop 20 is already in the set state as described above, the logic of the Nant gate 26 is established and the output becomes "0". Therefore, even at this point, the reception to the controller B is still due to the discrimination signal JR2. teeth"'
0, and the access request from controller B is not accepted.

Next, when the memory start signal MSA of "0" level is outputted from the controller A as shown in FIG. It is held until becomes 0''.

Then, the memory cycle ends and the signal EMC becomes the second
As shown in Fig. 1, when < “o” is reached, this signal “0”
is inverted by the inverter 18, and since the flip-flop 14 is in the set state at this time, the Nant gate 21
is established, the output of the gate 21 becomes '0'' as shown in FIG. 20 are reset together.

Therefore, the reset output enable signal of the flip-flop 20 returns to '1' again at this point, as shown in FIG. 2e.

As a result, the output of the NAND gate 26, which had been outputting "0" until the flip-flop 20 was reset, becomes 1.
At this point, controller B accepts the discrimination signal JR2 force 1'' for the first time, and controller B's access request is accepted.

Furthermore, since the flip-flop 20 is reset, the output of the Nant gate 28 becomes P0''', and the flip-flop 19 is directly set.

Then controller B sends "0" as shown in the second diagram.
``When the memory start signal MSB of the level is issued, the flip-flop 15 is directly set, and this state remains until the end of the memory cycle, that is, the NAND gate 2
It is held until the output power of 2, n Q 97.

Next, within this period, controller A sends 910 again.
When the access request signal QA of 1+ is issued, the flip-flop 13 becomes set state, and at this time, since the flip-flop 19 is set state, the Nant gate 2
5 is established, and the determination signal JR1 becomes '0' for the first time as shown in FIG.

When the memory cycle end signal EMC becomes '0'' again, the output of the inverter 18 becomes 1'', and since the flip-flop 15 is in the set state at this time, the output of the Nant gate 22 becomes '0'. As shown in Figure 2
becomes f+ Ojl, flip-flop 15.19
Reset together.

Further, by resetting the flip-flop 19, the output of the NAND gate 25 becomes I+ 111, and therefore, the determination signal JR1 becomes ``1'' again as shown in FIG. is accepted.

In this way, when both controllers A and B issue access requests to the bulk memory, data can be transferred alternately in the order in which the requests are issued.

Therefore, even when it is desired to transfer data immediately, there is almost no waiting time and rapid data transfer is possible.

In addition, since multi-calling can be performed using hardware with a simple configuration, a program specific to multi-calling is not required, resulting in a very economically advantageous configuration.

In the above-described embodiments, a core memory is used as an example of a static storage device constituting the bulk memory, but the present invention is not limited to this, and static storage devices such as an IC memory or a wire memory may be used. It is also possible to easily apply the present invention in various ways without departing from the gist of the present invention.

As described in detail above, according to the present invention, a static storage device is used as the bulk memory, and a logic circuit with a simple configuration allows memory cycles to be stolen in the order in which access requests are received from two active modules. Equipped with a function that alternately grants permission to occupy memory, it is possible to perform high-speed and efficient data transfer, and it is also very economically advantageous because multi-calls can be performed with the same program control as single calls. A bulk memory multi-call control method can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment. lL12, 16, 17, 18...Inverter,
13.14,15,19,20...Flip-flop, 21.22,23,24,25,26°27.
28...Nand Gate

Claims (1)

[Claims] 1 Means for using a static storage device as a bulk memory, and when an access request is issued from a first and second active module using this bulk memory, one memory cycle is alternately stored by memory cycle steal control according to the order of reception. 1. A bulk memory multicall control method, comprising: logic circuit means for granting occupancy permission.