JPS58200416A - Data waveform shaping circuit - Google Patents

Abstract

PURPOSE:To perform data waveform shaping with an optimum slice level, by comaring error data of plural periods with each other, and inverting the changing direction of the slice level when the error data increase. CONSTITUTION:An up-down counter 15 starts from an up-mode, and a slice level 3 rises up one step synchronously with the pulse of a clock signal 14. As a result, error factor of data increases to obtain A>B at a magnitude comparator 12, and then an FF13 is inverted. This drops the level 3 by a step, and therefore the error factor is reduced. Then the level 3 lowers by a step with the next clock pulse. In this case, if the error factor of data increases, A>B is obtained again to reset an up-mode. Such a cycle is repeated to make the level 3 follow on the basis of the optimum level with which the data errors are minimum. Thus it is possible to perform data waveform shaping with an optimum slice level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data punching circuit, and more particularly, to providing a data punching circuit suitable for a reproducing apparatus that reproduces a record carrier on which a digital information signal is recorded.

Along with advances in digital signal processing technology, advances have also been made in recording and reproducing technology for digitizing audio signals, etc.
In the audio field, digital recording and reproducing devices such as digital audio disks (hereinafter abbreviated as DAD) and digital audio tape recorders (hereinafter abbreviated as DAT) are being put into practical use. As the record carriers used for these recording/reproducing operations, DAD uses video disc technology, and DAT uses video tape recorder technology, and is characterized by extremely high recording density.

Because of high-density recording, the recording wavelength becomes short as a result, causing problems with waveform reproducibility during reproduction. This is an optical pick amplifier in DAD and DAT.
This is due to the frequency band limitations of magnetic heads, etc. in
No. 7 has a waveform with rounded corners during playback, and cannot reproduce a rectangular wave.

For this reason, it has conventionally been done to reproduce the original waveform by shaping the waveform using a level comparator, a Schmitt trigger, or the like. This is what is called data punching,
Next, a conventional example will be explained.

FIG. 1 shows an example of a data punching circuit using an ID level comparator.

A reproduced signal 2 is applied as an input signal to a level comparator 1, which compares the level with a slice level 3 and outputs the result as an output signal 4 in the form of a rectangular wave digital signal. The slice level 3 it: is also generally called a punching level or a reference voltage.

Figure 1 shows the input signal 2 and output signal 4 of the circuit in Figure 1a.
Input signal 2 has a waveform in which high frequency components are attenuated due to the influence of the head or pickup. As a result, it is no longer possible to reproduce the original waveform in high frequency parts.

-C may not be able to reproduce the original waveform due to the high-frequency attenuation described in -h and variations in the ridged tape or disc, especially,
Depending on the AT conditions when creating a master disc, the DC component of the reproduced waveform may vary greatly. Conventional data punching circuits cannot follow such fluctuations, so they are still unable to reproduce the original waveform, resulting in data errors.

The present invention takes the above-mentioned problems into consideration and provides a data punching circuit that changes the slice level accordingly while monitoring whether the data is correct or incorrect.An example of the present invention will be described below. .

FIG. 2 is a block diagram showing an embodiment of the data punching circuit of the present invention, and parts common to the conventional example are given the same numbers.

The output signal 4 of the first level comparator 1 is sent to the demodulator 6
, an error detection circuit 6, and a first D/A converter 7, the signal is restored to an analog signal and becomes an output signal 8.

The error detection circuit 6 outputs an error flag 9 indicating whether the data is correct or incorrect, and the counter 1o counts the number of incorrect data. The counted result is sent to the latch 11 and the input terminal A of the magnitude comparator 12. The latch 11 holds the previous number of error data, and sends this to the input terminal B of the magnitude comparator 12 before rewriting. The magnitude comparator 12 compares the numerical values represented by the digital signals applied to the input terminals A and B, and if A>B, that is, the current number of error data is larger than the previous number of error data, the magnitude comparator 12 A trigger signal is sent to the flip-flop tube 13 to invert it. The amplifier down counter 15, which counts the clock signal 14 applied through the delay circuit 17, performs up/down switching according to the output of the free-knob flip 713. The contents of the up/down counter 16 are converted to slice level 3 by the second D/A converter 16.
and is applied to the first comparator 1.

In the case of DAD, the clock signal 14 is a signal (1) synchronized with the rotation of the disk (Rus/1 rotation), which offsets the increase in the number of error data due to scratches on the disk, and in the case of DAT. It is preferable to offset the increase in the number of erroneous data due to the gutter switching by using a signal (1 pulse/1 rotation) synchronized with the rotation of the cylinder (rotary head). If you do this, for example, D
In ADeC, for each rotation of the disk, the current 1
The magnitude comparator 12 compares the number of error data for one rotation with the number of error data for one previous rotation.

FIG. 3 is a timing diagram for explaining the operation of the data punching circuit of FIG. 2. The knob down counter 16 starts from the up mode and is at slice level 3.
is equal to the clock signal 14 by 1υ1 and rises by 1 step. As a result, the data talk rate increases, and A>B, so that 7 rip flows and B 13 are reversed. Therefore, the up/down collar/reverse 15 switches to the down mode (switching), and the slice level 3 goes down one step.This reduces the error rate, so the slice level 3 goes down one step by the next clock pulse, and the knob goes down. do.

At this time, if the data error rate increases, A>B again and the flip-flow knob 13 is reversed to return to the up mode. As the above-described cycle is repeated, the slice level follows the optimum value with the least data error while repeating one-period minute changes.

However, in the present invention, if the slice level is extremely shifted, all data becomes erroneous, and it is not possible to deal with a minute change when the number of erroneous data does not change at all. In such cases (for example, before starting playback), use another method to significantly change the slice level, find a slice level at which the data error rate is below a certain limit, and start from that level. It is preferable to leave the

As described above, the data punching circuit of the present invention automatically adjusts the slice level while monitoring the data error rate. Following changes in
', and can perform data punching at the optimal slice level. Practical - It is highly effective.

[Brief explanation of drawings]

Figure 1a is a circuit diagram of an example of a conventional data punching circuit;
The figures are signal waveform diagrams of various parts of the conventional example, FIG. 2 is a block diagram showing one embodiment of the data punching circuit of the present invention, and FIG.
The figure is a waveform timing diagram of each part of the embodiment described above. 1... Level comparator, 3... Slice level, 6... Demodulator, 60... Error detection circuit, 1o... Counter, 110 ...
・Uh, Sochi, 12...Magnitude comparator, 13@...Flip-flop, 14...
. . . Clock signal, 15 . . . Up/down counter, 17 . . . Delay circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (97

Claims (3)

[Claims] (1) Means for changing the slice level stepwise at approximately constant intervals; - Means for sequentially storing the number of words of error data during the above-mentioned cycle; and comparing the number of error data in a plurality of cycles. and means for reversing the direction of change in the slice level when the number of error data increases. (2) Data punching according to claim 1, wherein the period is synchronized with the rotation of the information recording disk] 1 path. (3) The data punching circuit according to claim 1, wherein the period is synchronized with the rotation of a cylinder equipped with a magnetic head.