JPS6180568A - Digital data reproducing circuit - Google Patents

Abstract

PURPOSE:To improve the error rate of the titled circuit by setting automatically an optimum threshold value in response to an output level from a VTR to set the optimum threshold value to various VTRs. CONSTITUTION:An output of a latch circuit 13 is halved by a D/A converter 14, the output is used as the threshold value and an output of a clamp circuit 2 is extracted by a comparator 3. A counter 6 is incremented by using a clock with a prescribed period, its output is fed to a comparator 4 via a D/A converter 12, compared with a peak value of the output of the clamp circuit 2, and the output of the counter 6 when the output of the converter 12 is nearly equal to the level of the peak value is latched to a latch circuit 13. The output of the circuit 13 is halved by the converter 14 and used as the threshold value. The similar operation is repeated and data setting the optimum threshold value is stored always in the circuit 13.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to a PI using a VTR as a recording device, for example.
The present invention relates to a digital data reproducing circuit applied to a CM tape recorder.

[Conventional technology]

The V
TR is used to record digital audio signals on magnetic tape. At the time of reproduction, a signal having a level higher than a predetermined value is extracted from the output of this pseudo video signal output from the VTR. By extracting the output of the VTR with a level higher than a predetermined value in this way, the digital audio signal data superimposed on the pseudo video signal is shaped into a pulse waveform.

The optimal dark value for extracting the VTR output is a level in the center of the amplitude of the digital audio signal superimposed on the pseudo video signal. If a level reference signal is inserted into the pseudo video signal, the optimum darkness value is set based on this level reference signal. However, if the level reference signal is not inserted, it is not possible to set the optimal darkness value based on the level reference signal. For this reason, the darkness value in such cases has conventionally been set manually.

[Problem that the invention seeks to solve]

The output level of a VTR differs depending on the model.

Further, even within the same model, there are variations in output level from machine to machine. Therefore, if the VTR machine used for playback is different, the optimal darkness value level will also be different.

If the level S vehicle signal is not inserted in the data, the dark value is manually set and fixed at the set level, as described above. Therefore, the level of darkness value is
Each time you change the VTR, you have to manually reset the settings. However, it is very difficult to manually set the optimum value. Furthermore, if the dark value level is manually fixed in this way, the output level of the V T'R may fluctuate, and the optimum level of the dark value may fluctuate or 1. It is not possible to deal with cases where the dark value setting level fluctuates due to fluctuations in power supply voltage, etc. If the level of the dark value is not set to the optimal value, the error rate will deteriorate (.Also, if the level of the dark value is far from the optimal value, the digital audio signal data cannot be played back. becomes impossible.

Therefore, an object of the present invention is to automatically set the optimum darkness value according to the output level from the VTR, thereby making it possible to set the optimum darkness value no matter what kind of VTR is used. Can deal with fluctuations in VTR output level 1. It is an object of the present invention to provide a digital data reproducing circuit whose dark values are not affected by fluctuations in power supply voltage.

(Means for Solving the Problems) The present invention includes a clamp circuit 2, a counter 6 that performs a counting operation using a clock every predetermined period, and a first D/A that converts the output of the counter 6 into an analog signal. The output of the first D/A converter 12 is compared with the output of the first D/A converter 12 and the first D/A converter 1.
A detection circuit 4 detects that the output of the clamp circuit 2 exceeds the peak value of the output of the clamp circuit 2, and stops the counting operation of the counter from the output signal of the detection circuit 4.
A control circuit 7 that causes the latch circuit 13 to latch the output of the counter at that time, a second D/A converter 14 that converts the output of the latch circuit 13 into an analog signal, and an output of the second D/A converter 14. This is a digital data reproducing circuit which is supplied with the output of the clamp circuit 2 and further includes a comparator circuit 3 which outputs a digital signal.

[Effect]

The output of the latch circuit 13 is set to 1 by the D/A converter 14.
/2 and converted to an analog signal, and this D/A
The output of the converter 14 is set to the dark value, and the clamp circuit 2
The output of is extracted by comparator 3. The counter 6 is counted up by a clock having a predetermined period, and the output of the counter 6 is converted into an analog signal by the D/A converter 12, and compared with the peak value of the output of the clamp circuit 2 by the comparator 4. As the counter 6 counts up, the output of the D/A converter 12 approaches the peak value of the output of the clamp circuit 2 (.

The output of the counter 6 when the output of the D/A converter 12 becomes approximately equal to the level of the peak value of the output of the clamp circuit 2 is latched by the latch circuit 13.

The output of the latch circuit 13 is halved by the D/A converter 14 and converted into an analog signal, which is then used as a dark value. Similar operations are repeated, and data for setting the optimal darkness value is always stored in the latch circuit 13.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 indicates a VTR.

For example, 16 binoto digital audio signal data superimposed on a pseudo video signal is recorded on a magnetic tape mounted on the VTR 1. Audio signal data superimposed on this pseudo video signal is output from the VTRI, and this output is supplied to the clamp circuit 2. The amplitude level of the audio signal data on this pseudo video signal is
From the maximum value to the minimum value, for example, the reference value is 1.0. A clamp circuit 2 clamps the level of the pseudo video signal, and the output of the clamp circuit 2 is supplied to a comparator 3 and also to a comparator 4.

On the other hand, a vertical blanking pulse in the pseudo video signal is supplied from the terminal 5 to the clock input terminal of the counter 6, and also to the counter controller 7 and the gate circuit 11. The counter 6 is, for example, a 4-bit counter, and preset data is loaded into the counter 6 under the control of a load pulse supplied to the counter 6 from a load pulse generating circuit 8. The load pulse generation circuit 8 is supplied with a power-on signal and a dropout detection signal from terminals 9 and 10, and is also supplied with a control signal from the counter controller 7. At power-on or when dropout is detected, preset data (1
000) is loaded into the counter 6. When a control signal is supplied from the counter controller 7, the precent data (Ol 10) is loaded into the counter 6.

The data output of the counter 6 is supplied to the D/A converter 12 and also to the latch circuit 13. The output of the D/A converter 12 is supplied to the comparator 4. D/
The A converter 12 converts the output of the counter 6 into an analog value. For example, the output of counter 6 is (0110)
, it is converted to an analog value of 0.6 V, and (1000
), it is converted to an analog value of 0.8■. The output of the counter 6 converted into an analog value and the output of the clamp circuit 2 are compared by a comparator 4.

The output of the comparator 4 is supplied to a counter controller 7. The carry output of the counter 6 is supplied to the counter controller 7 . When the output of the D/A converter 12 becomes larger than the output of the clamp circuit 2, the counter controller 7 generates a counter signal and a control signal for the load pulse generating circuit 8 from the output of the comparator 4. Further, when a carry is output from the counter 6, a counter stop signal and a control signal for the load pulse generation circuit 8 are similarly generated by the counter controller 7.

The counter stop signal is supplied from the counter controller 7 to the counter 6 and also to the gate circuit 11. The control signal is supplied from the counter controller 7 to the load pulse generation circuit 8. When the counter stop signal is supplied to the counter 6, the counting operation of the counter 6 is stopped. At this time, the gate circuit 11 is opened by the counter stop signal supplied to the gate circuit 11, and a vertical blanking pulse is supplied to the latch circuit 13 via the gate circuit 11. As a result, the output data of the counter 6 at this time is latched into the latch circuit 13.

When the output data of the counter 6 is latched by the latch circuit 13, a control signal is supplied from the counter controller 7 to the load pulse generation circuit 8, and the preset data (011, 0) is loaded into the counter 6.

The output of the latch circuit 13 is shifted by 1 bit, multiplied by 1/2, and supplied to the D/A converter 14. The D/A converter 14 converts the output of the latch circuit 13 multiplied by 1/2 into an analog value. For example, when the output of the latch circuit 13 is (0110), it is converted to an analog value of 0.3V, and when the output of the latch circuit 13 is (1000), it is converted to an analog value of 4 V.

The output of the D/A converter 14 is supplied to the comparator 3, and a threshold value for extracting digital audio signal data is set by the output of the D/A converter 14. The output of comparator 3 is supplied to output terminal 15, and output terminal 1
5, a reproduction output shaped into a pulse waveform is taken out.

The setting of the dark value from which digital audio signal data is extracted in this embodiment will be explained below.

When the power is turned on, the precent data (10
00) is loaded, and the preset data (1000) is latched into the latch circuit 13.

From the clamp circuit 2, the minimum value E of the data shown in FIG.
A pseudo video signal having an amplitude of, for example, 1.0 square meters between 0 and the maximum value E3 is output.

The preset data of counter 6 when the power is turned on is (1,0
00>. The output level E2 of the D/A converter 12 when the power is turned on is an analog value of 0.8 V at the time of preset data (1000), and the output of the D/A converter 14 is 1/2 of this, 0.4 V. be. Clamp circuit 2
The output is extracted using the output E2 of the D/A converter 14 as a threshold value.

At this time, the output level E2 of the D/A converter 12 is 0.
8V, the maximum value E3 of the pseudo video signal is level 1. O.V.
lower. Therefore, the data on the counter 6 is counted up at the next vertical blanking pulse.

When the vertical blanking pulse is supplied, the output of the counter 6 becomes (1001). At this time, clamp circuit 2
Since the data (1000) is stored in the latch circuit 13, the output of the D/A converter 14 is 0.4■
is taken out as a dark value. Output of counter 6 (10
The analog value of 01) is 0.9 V, and the maximum value E of the pseudo video signal is level 1. Lower than OV. Therefore, the data of the counter 6 is counted again by the next vertical blanking pulse.

In this way, the data of the counter 6 is incremented each time a vertical blanking pulse is supplied, so that the output level of the D/A converter 12 increases and approaches the maximum value E3 of the pseudo video signal. D/A converter 12
Until the output of exceeds the maximum value E of the pseudo video signal,
The output of 0.4 V of the D/A converter 14 formed by the preset data stored in the latch circuit 13 is set as a dark value, and the output of the clamp circuit 2 is extracted.

When the output level of the D/A converter 12 exceeds the maximum value E of the pseudo video signal, the operation of the counter 6 is stopped.
The output data of the counter 6 at this time is latched by the latch circuit 13. The analog value of the data latched by this latch circuit 13 is approximately equal to the maximum value of the pseudo video signal. Therefore, the output of the D/A converter 14 is at a level approximately at the center of the amplitude of the data of the pseudo video signal, and the output of the clamp circuit 2 is extracted at a level approximately at the center of the amplitude of the data of the pseudo video signal. When the output data of the counter 6 is supplied to the latch circuit 13, the counter controller 7
A control signal is supplied from the load pulse generating circuit 8 to the load pulse generating circuit 8, and the data of the counter 6 is reloaded to the preset value (0110).

The analog value of this precent value (0110) is 0.6v
Then, the maximum value E of data output from the clamp circuit 2,
lower. Therefore, each time a vertical blanking pulse is supplied, the data of the counter 6 is counted up, and the D/
The output level of the A converter 12 approaches the maximum value of the pseudo video signal (During this period, the output of the clamp circuit 12 is set to a dark value from the data stored in the latch circuit 13, and the output of the clamp circuit 2 becomes D The output of the /A converter 14 is extracted as PJ (!

When the output level of the D/A converter 12 exceeds the maximum value E of the pseudo video signal, the operation of the counter 6 is stopped.
The output data of the counter 6 at this time is latched by the latch circuit 13. If there is no variation in the output level of the VTR 1, the latch circuit 13 stores data similar to the previously set data. If a fluctuation occurs in the output level of the VTR 1, the data in the latch circuit 13 is changed and rewritten to data whose analog value is approximately equal to the maximum value of the pseudo video signal.

In this way, the analog value of the data stored in the latch circuit 13 is always approximately equal to the maximum value of the pseudo video signal output from the clamp circuit 2. Therefore, D/
The output of the A converter 14 is always at a level approximately at the center of the amplitude of the data of the pseudo video signal, regardless of fluctuations in the output level of the VTR 1.

On the other hand, if dropout occurs, preset data (1000) is loaded into the counter 6 and the dark value is set to 0.4V. In addition, if the level of the maximum value of the data of the pseudo video signal is extremely high (and an overflow occurs in the counter 6, the counter 6 is stopped at the maximum value data (1111) of the counter 6, and this data The value is set.

Although the number of bits of the counter 6 in the above embodiment is 4 bits, the number of bits of the counter 6 is not limited to 4 bits. Furthermore, the data preset in the counter 6 can be changed as appropriate.

〔Effect of the invention〕

According to this invention, the level of the peak value of the data of the pseudo video signal is detected, and the dark value is approximately l/2 of this peak value.
It is always set so that Therefore, the optimal darkness value is always set according to the output level of the VTR. However, the point of change in the darkness value is within the vertical blanking interval. Therefore, you can set the optimal darkness value no matter what kind of VTR you use, and even if the output level of the VTR fluctuates,
Along with this, the darkness value is automatically reset to the optimal value. Therefore, according to the present invention, it is possible to improve the error rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram used to explain the embodiment of the invention. 1: VTR12: Clamp circuit, 3.4: ': 1 amparator, 5: Vertical synchronization signal input terminal, 6: Counter, 7
: Counter controller, 11: Gate circuit, 12,1
4: D/A converter, 13: latch circuit, 15 two output terminals.

Claims (1)

[Claims] a clamp circuit, a counter that performs a counting operation using a clock every predetermined cycle, a first D/A converter that converts the output of this counter into an analog signal, and an output of the clamp circuit and the first D/A converter. a detection circuit that compares the outputs of the first D/A converter and detects that the output of the first D/A converter exceeds the peak value of the output of the clamp circuit;
A control circuit that stops the counting operation of the counter based on the output signal of the detection circuit and causes a latch circuit to latch the output of the counter at that time, and a second D/A that converts the output of the latch circuit into an analog signal. A digital data reproducing circuit comprising: a converter; and a comparator circuit supplied with the output of the second D/A converter and the output of the clamp circuit and outputting a digital signal.