JPS5820029A - Analog-to-digital converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter which is free from an error caused by offset voltage, by feeding the sampling value of an analog signal to a voltage follower type comparator and performing the sampling with addition of the offset voltage of the comparator. CONSTITUTION:For an A/D converter containing a D/A converting circuit, a comparator and a sequential comparator, an end of plural capacity elements 22 of the D/A converting circuit to the negative input of a comparator 23. At the same time, the other end of the element 22 is connected to a switch SW24 that switches an input signal Vin between reference potential VR and the earth potential. The positive input of the cmparator 23 is connected to a switch SW25 which performs the switching between the potential VR and the earth potential. Then an output signal is fed back to a negative input via a switch SW21. The SW21 is closed with the SW24 and SW25 connected to the signal Vin and the earth, respectively. Then the SW21 is opened, and the SW24 is earthed. The signal Vin is sampled with the capacity 22, and the polarity of the Vin is decided. According to the positive or negative polarity of the Vin, the SW25 is connected to the potential VR or the earth. Then a part of the SW24 is earthed with the other part connected to the VR. The SW21 is closed and then opened, and the comparator 23 performs a sequential comparison. Thus the offset is eliminated for the A/D conversion.

Description

[Detailed description of the invention] This fIA- is an analog digital, A/hensei 6 (hereinafter referred to as A
The present invention relates to a converter for a single reference potential when converting a bi-false signal *JAs using a charge redistribution method.

The MuDR converter using the charge redistribution method usually has the configuration shown in Figure 1. -1 is a D-direct conversion circuit, or a successive ratio IIR circuit consisting of a register, etc., and an 8#i ratio. This figure shows an IIR device. In this ζ, the capacitive elements connected in parallel that constitute the D-DC conversion circuit l are successive ratio IIR
Circuit S sequentially disconnects the connection 9111I and compares II8
Obtain the output signal Voutl from.

The excitation field will be explained below with reference to diagrams R1 to #Is.

The S diagram reference switch 1lt- is closed, and the polarity of the input 11ff (hereinafter referred to as Vja) is determined by the ratio soft 618.

ζHere, the polarity is determined using the offset voltage (hereinafter referred to as Voff 1!) t-reference of the ratio I#R-18. Originally, the polarity 4IlI constant of input No. 111 Vim is
This is preferably done by comparison with ground potential, but s
In tA shape, the ratio is 4m! It is difficult to make the Voff 1 of the device completely equal to the dominant potential due to the structure of the element itself.Therefore, in this case, it is convenient to set the field positive when Vis > is larger than Voff, and the field responsible when it is small. I will call it.

Turn down the switches 11 connected to the lower electrodes of the capacitive elements 14 of am constituting the Ja & 5D-A conversion circuit for which Via is determined to be positive to
Win, which is an analog inertial force, is sampled into the capacitive element 14.

Referring to FIG. 8, in FIG.
The number of capacitive elements 14 shown is the sum total of the number of capacitive elements 14, and the switches 11 and 111 are omitted from the drawing.
All one poles are connected to the sensitivity vB.

After that, open the switch l1 (, $ljl), and while supplying the charge t-tS to the lower electrode of the capacitor section 15, some of the capacitors 17 are grounded, and the other capacitors 16fg Connected to the ground potential and successively compared with the ground potential to obtain digital
No. 8 t Vout 4 In Figure 4, 6 and Figure 5, the voltage vc generated at the positive input layer of the ratio lIm device 18 can be immediately determined by the following equation.

Note that the capacity of the capacitor 15 (the sum of the capacitances of the valley jills 14) is 0 mu, and the capacity of some of the capacitors 16 is toX.

Let the capacitance of the other capacitive element 16 be t-ay.

Q = OA(Vjn-V,R)-0X(VO-VB)
+0YV0 18 Voltage V□a generated at this positive input terminal
Voff is compared and the values of both sides are made equal. The switches 1is (FIG. 3) connected to the lower electrodes of the capacitors 1 and 1 are respectively set to the ground voltage side, and the analog human power bias gyfon is sampled to the capacitor 14.

After that, the stone n mentioned in # is determined to be positive, and the switch 11 is opened to hold the charge in the lower electrode of the element Ji@Is, and some of the Sm elements 16 are set to the reference potential, and the others are set to the reference potential. Connect the capacitive element to ground potential 1. A digital signal is obtained at the Vout terminal by successive comparisons with the ground potential (see FIG. 5).In this case, the voltage v□ generated at the positive input terminal of the comparator can be determined as shown in the following equation. In addition, here, 0m,
OX and OY represent the same capacitance as shown in equations (1) to (3), respectively.

Q -OAV in -0X(VOVK)+0yV0
4l-OAVO0XVR (4) Compare this v□ and Voff, make the values of both sides equal, and determine the OXO value using the formula below. Conversion-
The polarity of the digital signal 111 outputted from 19 is determined based on the offset voltage of the comparator, and the value of OX or CY is determined, and accurate A-Di detection is one step away. . The offset voltage of such A-D conversion is prevented as described above, and also causes a difference in conversion sensitivity.

In view of the above-mentioned problems of the prior art, the present invention uses a single reference voltage with less error due to offset voltage. A-
The purpose is to provide DR exchange m. The object of the present invention is to
-jII of each capacitive element is connected to the negative input terminal of the comparator, and the other capacitors are respectively switched to the reference potential, input signal, and ground potential. I was late to Route 1111, and m
The positive input layer of the IR device is connected to the reference potential and the ground potential, respectively, and connected to a four-way quadrature circuit, and the ratio [! is connected so that the output of t is fed back to the negative input terminal at a predetermined time.
19 is achieved in an analog-to-digital converter with tf# value. That is, in the present invention, when performing analog mvt sampling, the offset voltage of By performing the sampling ^^ and for the ratio 4Rt offset voltage of the sampled input signal, the resulting digital 1! I: Eliminate the sensitivity difference due to the offset voltage of i5.

Hereinafter, with reference to FIGS. 6 to 11, the present invention will be described.
6 Explaining the operation of the A-D converter. ! Refer to figure g6 In the present invention, one end of the ll1iiiao capacitor 83 is connected to the negative input terminal of the comparator is, and the other end is connected to the input signal '@ (hereinafter referred to as Via), #teruwaki position (hereinafter VR ) and are connected to a switch z4 which can be switched to the ground potential, respectively.Furthermore, the positive input trend of the ratio IIR device s8 is
In addition, the negative input terminal of the comparator 28 is connected to the switch 85 which can be switched to R and ground potential.
The connection is made through the switch ill which returns the output signal at a fixed time.
Connected to the t-ground potential and input the analog signal vAfl with the circuit configuration shown in Figure J@7.Here, S6 indicates a capacitor whose capacitance is the sum of six violets of each capacitive element s8. .

Refer to FIG. 8. Thereafter, the switch 21t is opened, and the switch 14 (FIG. 6) is then connected to the ground potential. Input signal V4
The capacitance of a is sampled at the upper electrode of section s6, and a voltage VD expressed by the following formula is generated at the negative voltage of comparator 88. 86
Let the offset voltage tVoff be tVoff.

Qw OA (Voff - V f ) = 0AVD
t7) VD -Voff -Vin
(81 where input 1i
! The value obtained by adding Voff to the inversion 1 of vVin and V
Since the ratio with the output signal Voutl is 12, the offset voltage Voff of the comparison 428 is canceled out, and the polarity of the analog signal 1M ifl can be determined almost accurately with respect to the peak potential.

Refer to Figure 9. The operation mode is divided depending on the polarity of the determined Via, and the switch m s (
j1g6 diagram) to the # line potential, and switch 81 (4@
) is closed, and the analog human input signal VfiIII is sampled into the capacitive part z6.

See Figure 11 for the switch! 1 (IA6 diagram) and switch 8
4 (Fig. 46) is grounded, and the other part is set to v8.
Connect to and perform successive approximation with the reference potential. In the figure, the moving part 87 of the capacitor part is connected to V and the part 88 is connected to the ground potential.
Teru.

Here, the voltage (2o) generated at the negative input terminal of the ratio #R device SS is expressed as in the following equation. In addition, # capacity of storage section B7 is OXs
Volume 1kt16 B 8 of 6 violet lay OQ = O
A(Voff+VB-Via)=(0)((V□-VB
)+OyV□ #1j=OAV0 0XVg
(Q), and the direct t-value of both ministries is determined, and OX Od is determined by the following formula.
s (FIG. 6) is connected to the ground potential, switch 2 (FIG. 6) t- is closed, and the analog input signal Vln is sampled into the capacitor section 16.

Refer to FIG. 11. Thereafter, as in the case where the polarity of the input signal Win is positive, the switch BICIiB is opened and the switch 84 (
Figure 6) is connected to ⇠ or ground potential and the output No. 11 Vout is obtained by successive comparison ◎Here, the ratio 41
The voltage v□ generated at the negative input terminal of the doubler 38 is expressed as in the following equation. 2, OX, OY represent 1m of equation (9) to 1 and iWJ.0Q=0.1(Voff-W
in)=OX(V□ Vl)+OyVg @-OA V
o UX V B (12) Compare the voltage generated at this negative input terminal■0 and VB+Voff, make it 11tt*L for both, and use the following formula to calculate 0y
(Z) value is determined.

By the successive ratio fi + operation until OX play KOY is determined] digital output is obtained and 5A-DR
The exchange is complete.

Therefore, according to the single-shot tIAK, the offset voltage of the comparator is canceled and compensated for in the input signal VjaO polarity judgment and successive approximation operation, so that the high S direct current conversion can be performed in nine sleeps. It is.

Furthermore, according to the present invention, formula (3), formula a9, and (6)
As is clear from the relative softness of formula and formula 04, in order to perform a successive comparison with #line potential Vi, #irradiation potential with a rate of − is used.
-AIA can be performed accurately and with an easy-to-understand structure using the charge redistribution method.

In addition, in the present invention, 1gl of digital-to-analog conversion
The circuit includes a plurality of capacitive elements connected in parallel and their terminal switching circuits.

M9, 4) As a continuous circuit that determines the terminal potential tgJ,
In the above real example, 2- is a simple switch circuit t-
Although this is commonly used, the invention of the present invention is not intimidated by this. (cut) Tora 7 as a general IIk connection circuit in Kagami Town
4a1rJ's premature explanation 1m is the configuration of the MuD transformer fII by the charge redistribution method, and the S figure to 55 is the conventional MuD transformer. 6 to 11 respectively show the operating principle of the human converter according to the present invention. In the figure, l is the D-A conversion path and , Jl.
e Z 8 e s8 is ratio @as 11m1mmsxm
sllmlmm5x? % 14*mB is 5tac child, Z
5? k 6 a t1B61B? , s8 is g consisting of one or 411 capacitive elements connected in parallel.
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Claims (1)

[Claims] sP%A to an analog-to-digital converter having a digital to analog R conversion 1gl#II, ratio@S, and successive ratio IIR circuit, the digital to analog converter circuit is a capacitive element connected in parallel; Consisting of a switching connection circuit for the heavy duty element, one of the a# quantity detectors is connected to the negative input layer of the comparator, and the other end is connected to the reference potential, the input signal,
Ii! is connected to a connection circuit that switches to the ground potential, and also switches the positive input trend of the front C comparator to the reference potential and ground potential, respectively! I is connected to the connection line 1gi, and causes the output of the auxiliary screwdriver to be applied to the negative input layer kRffi at a predetermined time.
An analog-to-digital transformer featuring the best of both worlds.