JPS58197746A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain the IC applyable not only to input/output of a logic level, but also applyable to input/output of a non-logic level at the device having macros of the plural pieces provided on a semiconductor chip, input/output pads of the plural pieces provided around the chip, and a middle cell to connect between them by a method wherein a through channel of at least one piece is provided to the middle cell. CONSTITUTION:At the master slice system IC, common element patterns given the name of the macros are formed to be arranged in the matrix type on one semiconductor chip previously, and mutual wirings between the macros are performed complying the developed kind. Therefore the through channel 210 according to a metal wiring, a terminal 211 to connect between an inside circuit consisting of the macros, and a terminal 212 to connect between an input/output pad connecting terminal 108 are provided to the input/output cell 100. Moreover an inside earthing bus 220 to apply the reference electric potential to the inside circuit, an earth lead-out wire 230, a terminal 231 to connect the lead-out wire 230 to the terminal 108, and an electric power source bus 240, etc., are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a master slice type semiconductor integrated circuit device.

Large-scale integrated circuits (LaI3) for computers, terminal devices, and other general control devices are being actively developed.These semiconductor integrated circuit devices have a particularly strong tendency to be produced in high-mix, low-volume production, which reduces manufacturing costs and shortens the manufacturing period. Manufacturing by the rounding master slice (master 5 slice 3 method) is often used.

In a master slice type semiconductor integrated circuit device, a common element pattern called a macros is created and arranged in advance in a matrix shape on one semiconductor chip, and a dedicated wiring mask is created depending on the product to be developed. A semiconductor integrated circuit device having a desired circuit function is completed by interconnecting the macrocrosses.

FIG. 1 shows a simplified configuration of a master slice type semiconductor integrated circuit device.

In the figure, 10 is a semiconductor chip, around which a plurality of input/output pads 11 for connection with input/output bins are arranged, and further, inside the input/output pads 11, an input/output cell 12 which is an intermediate cell is arranged. has been done. 13 is Macross,
They are arranged in a matrix at the center of the semiconductor chip 10. For example, when the logic gate cell is configured with 0MO8, the macros 13 includes multiple NMO8) Tunisters and PMOS.
Transistors are placed in advance, and connections between transistors are made in the master slicing process.
NAND gates, flip-flops, etc. will be realized.

Reference numeral 14 denotes a predetermined channel for nine wirings between the macros 13 and between the macros 13 and the input/output cell 1.
The wiring channel 14 is provided between the macros 13 and the input/output cells 12, and interconnection between the macros 13 and the input/output cells 12 is performed using the interconnection channel 14, thereby achieving the desired semiconductor integration. The circuit is completed.

Here, the function of the input/output cell 12 serving as an intermediate cell will be briefly explained. The input cell is an interface circuit for introducing signals from the outside of the semiconductor integrated circuit into the inside of the semiconductor integrated circuit, that is, the macrocross.
If the inside of the semiconductor integrated circuit is composed of 0M08 circuits, the signal level is converted from the TTL signal level to the CMO8 signal level.

Next, the output cell is a rounded interface circuit that derives a signal from the inside of the semiconductor integrated circuit to the outside of the semiconductor integrated circuit.For example, from the CMO8 signal level inside the semiconductor integrated circuit to the 0TTL (l-8 Before performing level conversion, the output cell directly drives an external load, and generally has a much higher load driving capability than the internal macrocross 13.

FIG. 2 is an enlarged view of an input/output cell serving as an intermediate cell for a master slice, which has been frequently used in the past.

In FIG. 2, 100 indicates the entire input/output cell, and 200
is an input/output pad for connecting an external pin of the semiconductor integrated circuit to the inside of the semiconductor integrated circuit.

101 is an input buffer, and 102 is an output buffer.

When using the input/output cell 10G for input, the terminal,
103 and terminal 108 are connected, and external notes are introduced into the internal macros through input/output pad 200, input buffer 101° terminal 104.

Next, when the input/output cell 100 is used for output, the terminal 106 and the terminal 108 are connected, and the output of the internal circuit is outputted to the outside of the semiconductor integrated circuit through the terminal 105, the output buffer 102, and the input/output pad 200. Ru. Note that the terminal 107Fi is a rounded control terminal that switches the output buffer 108 to a tristate (high impedance) state.

19. When the input/output cell 100 is used for both input and output, the terminal 103 and the terminal 108 are connected, and the terminal 10
6 and terminal 108 are connected.

Since such a conventional intermediate cell is intended to input or output a logic level signal, it is impossible to input or output a non-logic level analog signal.

In addition, conventional intermediate cells only have the function of inputting and outputting signals, and if the input/output bins are not used, the input/output bins cannot be used effectively.

The purpose of the present invention is not only to input and output logic level signals, but also to
An object of the present invention is to provide a highly conductive integrated circuit device equipped with an intermediate circuit that can also be used for non-logic level input/output.

Another object of the present invention is to provide a highly conductive integrated circuit device equipped with intermediate cells that can effectively use unused input/output bins.

The present invention is a rounded circuit that eliminates the disadvantages of the conventional intermediate cell as described above, and a through channel for rounding that performs non-logic level input/output to the intermediate cell. ^ It is said that being biased is 41 molds.

Furthermore, another feature of the present invention is that a ground lead-out line for turning an unused bin into an additional ground bin and a power lead-out line for turning an unused bin into an additional power supply bin are connected to the intermediate cell. By providing this, it is possible to make effective use of unused bottles.

The present invention will be explained below with reference to the drawings. In the following drawings, the same numbers as in Figure 2 indicate the same parts, and 9 indicates equivalent parts.

In FIG. 3, 210 is a through channel made of, for example, metal wiring, 211 is a round connection terminal that connects to the internal circuit consisting of a macro, and 212 is an input/output pad connection terminal 1.
This is a round connection terminal that connects to 08. 220 is an internal grounding path that provides a reference potential to the internal circuit made up of the macros through metal wiring; 230 is a grounding lead line that is made of metal wiring; 2
31 is a connection terminal for connecting the grounding drawer @230 to the terminal 108. Reference numeral 240 indicates a power supply bus for supplying a power supply potential to the internal circuit made of Shimacross through metal wiring, 250 indicates a power supply line formed by metal wiring, and 251 indicates a ninth connection terminal for connecting the power supply line to the terminal 108. The nine input/output cells 100 shown in FIG. 3, which are the intermediate cells of this embodiment, perform non-logic level input/output by connecting the terminals 212 and 108 in addition to conventional logic level input/output functions. be able to.

By connecting terminal 231 and terminal 108,
Unused bins not used for signal input/output can be used as additional ground bins.

Furthermore, connecting the terminal 251 and the terminal 108
An unused bin that is not used for signal input/output can be used as an additional power supply bin.

Which of the above functions can be achieved in the input/output cell 100, which is an intermediate cell, is determined by creating a wiring mask for the input/output cell at the same time as creating a wiring mask for each product. You can decide freely.

FIG. 4 shows an example of wiring when this embodiment is used as an analog input cell.

In the figure, 300 indicates an internal circuit portion composed of macros. 31O is an analog comparator, 3
11 and 312 are its input terminals, and 313 is its output terminal. In the figure, one terminal 21 of the through channel 210
2 is connected to the terminal 108 of the input/output pad, and the other terminal 211 is connected to one input terminal 311 of the analog comparator 310. Therefore, in this embodiment, the input/output cell 100 functions as an analog input cell, and the output terminal 313 of the analog comparator 310 receives the analog signal applied to the input terminal 311 and the analog signal applied to the input terminal 312. The comparison result with the analog signal is output.

FIG. 5 shows an example of wiring when this embodiment is used as an analog output cell.

In FIG. 5, 32 (l operational amplifiers), 321 .
322 is an input resistor, a feedback resistor, and 3231.3
24 are an input terminal and an output terminal of the operational amplifier, respectively. In FIG. 5, the nine analog signal 3 applied to the input terminal 323 is amplified and outputted to the output terminal 324. The output terminal 324 of the operational amplifier 320 is connected to the input/output pad 200 via the terminal 211, the through channel 210 terminal 212, and the terminal 108. Therefore, in the JIK5 diagram, the input/output cell 10G functions as an analog output cell.

In addition, the configuration of this example! ! The through channel 210, which is one of the cables, may be a simple wire connecting the terminals 211 and 212, or as shown in FIG.
Even if it includes a series circuit or a parallel circuit 215 formed of resistors, diodes, transistors, etc. provided between the input enclosures, it is sufficient that the input enclosure does not impair the through function as an output.

Figure JIII shows an example of wiring when this embodiment is used as a grounding reinforcement cell.

In the 7th FIA, the internal ground bus 220 is connected to the ground conductor 2301 via the terminal 2311 and the terminal 108.
Connected to 00. Therefore, in the jIT diagram, the input/output cell 100 functions as a ground reinforcement cell.

FIG. 8 shows an example of the arrangement when this embodiment is used as a power supply reinforcement cell.

In FIG. 8, the internal power bus 240 is connected to the power supply line 250.
, terminal 2511 is connected to the input/output pad 200 via the terminal 108. Therefore, in Fig. 8, input/output cell 1
00 functions as a power enhancement cell.

Note that although the embodiment of the present invention shows the case where there is one through channel, this is not always the case! A fixed number of through channels may be provided, such as dividing into an input-only through channel and an output-only through channel depending on the situation.

(9) Regarding the ground lead wire and power lead wire, if there are two or more systems of internal ground buses and power busses, multiple ground lead wires and power lead wires may be provided. Furthermore, the lengths of the through channel 210, the grounding lead wire 230, and the power supply lead 9250#i may be zero.

That is, the connection terminals 211 and 212 may be the same terminal, or the connection terminal 231 may be provided at any point on the internal ground bus 22G. Similarly, achievement l&reiko 25
1 may be provided at any point on the internal power supply bus 240.

Furthermore, in the intermediate cell according to the present invention, it is not necessary to provide all of the through channels, ground lead wires, and power lead wires, and only the necessary ones may be provided.

As is clear from the above explanation, according to the present invention, the invention can be applied not only to the input/output of logic level signals, but also to the input/output of non-logic level signals. In the case of a semiconductor integrated circuit device based on this method, the effect is significant.

Furthermore, according to the invention, the intermediate cell has a signal input/output K1
Since the external pin that is not used for 1l can be used as a ground reinforcement pin for TFC, f/ can be used as a source reinforcement pin, so fluctuations in the ground level ↑'-source level of the internal circuit can be reduced, resulting in a more stable semiconductor integrated circuit device with 9-circuit operation. can be obtained.

[Brief explanation of the drawing]

1 FiA is a plan view schematically showing a master slice type semiconductor integrated circuit, Figure 12 is a circuit diagram of a conventional input/output cell in Stripe 1, and Figure 3 is an input/output cell according to an embodiment of the present invention. 4 is a circuit diagram when an input/output cell according to an embodiment of the present invention is used as an analog input cell, and FIG. 5 is a circuit diagram when an input/output cell according to an embodiment of the present invention is used as an analog output cell. 6 is a diagram showing a through channel according to another embodiment of the present invention, FIG. 7 is a circuit diagram when an input/output cell according to an embodiment of the present invention is used as a grounding reinforcement cell, and FIG. 8 is a diagram showing a through channel according to another embodiment of the present invention. 1 is a circuit diagram when an input/output cell according to an embodiment of the present invention is used as a power supply reinforcement cell. 11.200...I/O pad, 12,100...
Input/output cell, 13...Macross, 210...Through channel, 220...Internal ground bus, 230...Ground lead wire, 240...Power supply bus, 250...Power lead wire. Agent Patent Attorney 41st year of high school! Bright (1st m'JP; 4L figure

Claims (1)

[Claims] 1. A plurality of macros provided on a semiconductor chip;
A plurality of input/output pads provided around the line conductor chip, and provided at the thresholds of the macros and the input/output pads,
1. A semiconductor integrated circuit comprising an intermediate cell T-connected to the macrocross and the input/output capacitor, wherein the intermediate cell has at least one through channel. 2.4II#'Pfl The semiconductor integrated circuit according to the first term of the range, wherein the through channel is a metal wiring that directly connects the macrocross and the upper four input/output capacitors. 3. A plurality of macros provided on a semiconductor chip,
a plurality of input/output pads provided around the semiconductor chip, and provided between the macros and the input/output pads,
In the device comprising an intermediate cell connecting the macrocross and the input/output pad, the intermediate cell is a ground leader line connected to the inner S ground path that provides a reference potential to the macrocross; 1. A semiconductor integrated circuit characterized by having a power supply line connected to a power supply path that supplies a power supply potential to a macros. 4. A semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the intermediate cell has an input buffer or an output buffer.