JPS58197723A - Preparation of epitaxial wafer - Google Patents

Preparation of epitaxial wafer

Info

Publication number
JPS58197723A
JPS58197723A JP7943282A JP7943282A JPS58197723A JP S58197723 A JPS58197723 A JP S58197723A JP 7943282 A JP7943282 A JP 7943282A JP 7943282 A JP7943282 A JP 7943282A JP S58197723 A JPS58197723 A JP S58197723A
Authority
JP
Japan
Prior art keywords
film
substrate
resistance layer
high resistance
resistivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7943282A
Other languages
Japanese (ja)
Inventor
Shigeo Kotani
小谷　滋夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7943282A priority Critical patent/JPS58197723A/en
Publication of JPS58197723A publication Critical patent/JPS58197723A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To easily form a high resistance layer having a high resistivity with less dispersion thereof by forming it by vapor growth method on the other side under the condition that the one side of Si substrate is protected by polycrystalline Si film and oxide film. CONSTITUTION:A polycrystalline Si film 2 not including impurity is deposited on both sides of an Si substrate 1. An oxide film 4 is then formed at the surface of film 2. Here, the film 4 and film 2 are removed so that a single side of substrate 1 on which a high resistance layer 5 is formed is exposed. With the film 2 and film 4 remaining in such a condition considered as the protection film, the epitaxial growth processing is executed to the exposed substrate surface 1a. Thereby, a high resistance layer 5 is formed and finally an epitaxial wafer 10 can be obtained. According to this method, impurity in the substrate 2 can be protected from external diffusion. Moreover, generation of defect on the laminated layers during the epitaxial growth processing can be prevented. Accordingly, a resistivity of layer 5 can be set to a high value with less dispersion.

Description

【発明の詳細な説明】 〔発明の技術公費〕 本発明は、エピタキシャルウェハの製造方法に関する・ 〔発明の技術的背景とその間電点〕 高抵抗層をシリコン基板上に形成した所謂エピタキシャ
ルウェハは、例えばｐ＋ｔｔ１のシリコン基１［＃ｃ気
相成長処理を施して、エピタキシャル成長膜を設けるこ
とｋより得られる。しかし、このような所−生つエバを
使用する方法では、気相成長時に基板中の不純物である
ボロンがエピタキシャル成長層内に侵入するため、高抵
抗層の抵抗率のばらつ會が大きくなる欠点がある。[Detailed Description of the Invention] [Technical Public Funds of the Invention] The present invention relates to a method for manufacturing an epitaxial wafer. For example, a silicon base 1 of p+tt1 [#c can be obtained by performing a vapor phase growth process to provide an epitaxially grown film. However, in this method of using evaporated evaporation, boron, which is an impurity in the substrate, enters the epitaxially grown layer during vapor phase growth, resulting in large variations in the resistivity of the high-resistance layer. There is.

この欠点を解消するために、シリコン基板の表裏両面に
先ず熱酸化膜を形成し、次いで、熱酸化膜の一方を除去
して残存した酸化膜を、不純物の外部拡散防止膜として
、露出された基板上にエピタキシャル成長により高抵抗
層を形成する方法が開発されている。しかしながら、こ
の方法で７は、例えばｐｍの場合には、シ、リコン基板
を醸化した酸化膜中に多くのボロンの量が存在する。し
かも、気相成長時の水素遺元雰囲、気の作用によって、
熱酸化膜の膜厚が目減りするため、ボロンの外部拡散を
完全に阻止できない欠点がある。In order to eliminate this drawback, thermal oxide films were first formed on both the front and back sides of the silicon substrate, and then one of the thermal oxide films was removed, and the remaining oxide film was used as an external diffusion prevention film for impurities. A method of forming a high resistance layer on a substrate by epitaxial growth has been developed. However, in this method, for example, in the case of PM, a large amount of boron is present in the oxide film formed on the silicon substrate. Moreover, due to the hydrogen atmosphere and the action of air during vapor phase growth,
Since the thickness of the thermal oxide film is reduced, there is a drawback that external diffusion of boron cannot be completely prevented.

この欠点を解消するために、熱鹸化膜の代わりにＣＶ　
Ｄ　（Ｃｈｅｎｉｃａｌ　ｖａｐｏｒ　Ｄｅｐｏｓｉｔ
ｉｏｎ　）　−８ＩＯ１膜を形成するようにした方法が
開発されている。この方法では、気相成長時に伴うスＩ
Ｊツブ転位が発生するのでＣＶＤＩＩＩをデンシファイ
処理する必要がある。才た、ＣＶＤ　　８１０ｍｍ１！
特有の突起物が１μｍ程度成長した場合発生し晶い欠点
がある。このため、微細／ｆターンの形成が要求される
所謁超ＬＳＩとしてのエピタキシャルウェハの製造には
適さない問題がある。In order to overcome this drawback, CV
D (Chenical vapor deposit)
ion ) -8IO1 film has been developed. In this method, the I
Since J-tube dislocation occurs, it is necessary to densify CVDIII. Excellent CVD 810mm1!
There is a crystal defect that occurs when specific protrusions grow to about 1 μm. For this reason, there is a problem in that it is not suitable for manufacturing epitaxial wafers as so-called VLSIs that require the formation of fine/f-turns.

この突起−の発生を阻止するために、チツ化膜（Ｓ’１
Ｎ４）をＣＶＤ−８ｉ０＊Ｉ！（７）代わりｍ形成する
ようにした方法も開発生されている。この方法では、チ
フ化膜とシリコン基板とのノ（メタル構造のために、チ
ツ化膜による応力が加わり、高抵抗層の厚さが２０声ｍ
以上に達すると所謂シャローピット等の積層欠陥が発生
するＯ著しい場合には欠陥の密度は、１０ｓケ／−以上
にもなる。その結果、デバイス形成時の耐圧不良になる
欠点がある。In order to prevent the formation of these protrusions, a silicon film (S'1
N4) to CVD-8i0*I! (7) Instead, a method in which m is formed has also been developed. In this method, the thickness of the high-resistance layer is reduced to 20 mm due to the stress caused by the nitride film due to the metal structure between the nitride film and the silicon substrate.
When this is reached, stacking faults such as so-called shallow pits occur. In severe cases, the density of defects reaches 10s/- or more. As a result, there is a drawback that voltage resistance is poor during device formation.

〔発明の目的〕 本発明は、低抵抗率の基板上に高抵抗率でしかも抵抗率
のばらつきの小さい高抵抗層を容易に形成することがで
きるエピタキシャルウェハ１の製造方法を提供すること
をその目的とするものである。[Object of the Invention] An object of the present invention is to provide a method for manufacturing an epitaxial wafer 1 that can easily form a high resistance layer with high resistivity and small variations in resistivity on a low resistivity substrate. This is the purpose.

〔発明のａ畳〕[A tatami mat of invention]

本発明は、シリコン基板の片面側を多結晶シリコン膜及
び酸化膜で保護した状態で、他面側にエピタキシャル成
長により、高抵抗率でしかも抵抗率のばらつきの小さい
高抵抗層を容易に形成することができるエピタキシャル
ウェハ＼の製造方法である。The present invention aims to easily form a high resistance layer with high resistivity and small variation in resistivity by epitaxial growth on one side of a silicon substrate while protecting the other side with a polycrystalline silicon film and an oxide film. This is a method of manufacturing epitaxial wafers that allows for.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について第１図乃至第ｓｒＩ！Ｊ
を参照して説明する。Embodiments of the present invention will be described below from FIG. 1 to srI! J
Explain with reference to.

先ず、第１図に示すような例えば抵抗率が０．１Ω１の
シリコン基板１を減圧ＣＶＤ装置内に設置する。次いで
、減圧ＣＶＤ装置内を約ｌ＠ｏｒｒの減圧状態に設定し
、ヘリウムにて２０１に希釈されたモノシラン８ｉＨ，
を供給する。この状態で基板１を約６００Ｃに加熱する
ことにより、第２図に示す如く、基板１の両面に、１０
０　Ａ　／　ｍｉｎの速度で不純物を含まない多結晶シ
リコンｌｌ！２を厚さ約１０００Ａ堆積する。First, a silicon substrate 1 having a resistivity of, for example, 0.1Ω1 as shown in FIG. 1 is placed in a low pressure CVD apparatus. Next, the inside of the reduced pressure CVD apparatus was set to a reduced pressure state of about 1@orr, and monosilane 8iH diluted to 201 with helium,
supply. By heating the substrate 1 to about 600C in this state, as shown in FIG.
Impurity-free polycrystalline silicon at a rate of 0 A/min! 2 is deposited to a thickness of about 1000A.

次に、このようにして得たウエノ＼３を、約ｔｏｏｏｃ
に設定された乾燥酸素雰囲気中に１０〜２０分間設置し
、多結晶シリコン膜２の表ｗｌｓ分を３００〜４００ｘ
酸化して第３図に示す如く、酸化膜４を形成する。Next, about toooc
The surface of the polycrystalline silicon film 2 was heated by 300 to 400x.
Oxidation is performed to form an oxide film 4 as shown in FIG.

次いで、１１ｇ４図に示す如く、後述する高抵抗層５を
形成する片面側にミラーラップ処理を施し、基板１が露
出するように酸化膜４及び多結晶シリコン膜２を除去す
る。Next, as shown in FIG. 11g4, mirror lapping is performed on one side on which a high resistance layer 5 (described later) will be formed, and the oxide film 4 and polycrystalline silicon film 2 are removed so that the substrate 1 is exposed.

この状態で残存した多結晶シリコン膜２及び酸化ｌＩ４
を保！ＩＩ膜さして、第５図に示す如く、露出された基
板表面１１に、エピタキシャル成長処理を施し、例えば
抵抗率が５０Ω国の凝抵抗層５を３０〜４０−ｍ形成し
、エピタキシャルウェハｐを得る。The polycrystalline silicon film 2 and oxide lI4 remaining in this state
Keep it! As shown in FIG. 5, the exposed substrate surface 11 is subjected to an epitaxial growth process to form, for example, a 30 to 40-m thick resistive layer 5 having a resistivity of 50 Ω, thereby obtaining an epitaxial wafer p.

而して、このエピタキシャルウェハの製造方法によれば
、エピタキシャル成長処理の際の水素還元雰囲気によっ
て酸化膜４の膜厚が目減りしても、その直下には多結晶
シリコン膜２が任在しているので、基板２内の不純物が
外部拡散するのを阻止することができる。しかも、多結
晶シリコン膜２は、不純物が存在しないアンドープの状
態のものであるので、基板２内の不純物の外部拡散防止
効果を更に高めることができる。また、多結晶シリコン
膜２及びその表面に形成された酸化膜４の熱膨張係数は
、基板２の熱膨張係数とほぼ等しい。このため、エピタ
キシャル成長処理の際に高抵抗層５中に積層欠陥が発生
するのを阻止できる。従って、２０−ｍ以上の肉厚を１
する高抵抗層５を容易に形成することができる。以上の
結果、高抵抗層６の抵抗率を高い値でしかもそのばらつ
きを小さく設定することができる。また、ＣＶＤ−５ｉ
ｏ、膜を形成する場合のようにデンシファイ処理を設け
る必要がないので、工程を簡略にすることができる。ま
た、高抵抗層５は、商い抵抗率を有して、しかもそのば
らつきが小さいので、この゛エピタキシャルウニハルを
使用することにより、高耐圧を有して優れた素子特性の
半導体装置を容易に得ることができる。According to this epitaxial wafer manufacturing method, even if the thickness of the oxide film 4 is reduced due to the hydrogen reducing atmosphere during the epitaxial growth process, the polycrystalline silicon film 2 remains directly below it. Therefore, it is possible to prevent impurities within the substrate 2 from diffusing to the outside. Furthermore, since the polycrystalline silicon film 2 is in an undoped state in which no impurities are present, the effect of preventing external diffusion of impurities within the substrate 2 can be further enhanced. Further, the coefficient of thermal expansion of the polycrystalline silicon film 2 and the oxide film 4 formed on its surface is approximately equal to the coefficient of thermal expansion of the substrate 2. Therefore, it is possible to prevent stacking faults from occurring in the high resistance layer 5 during epitaxial growth processing. Therefore, if the wall thickness is 20-m or more,
The high resistance layer 5 can be easily formed. As a result of the above, the resistivity of the high resistance layer 6 can be set to a high value and its variation can be set to be small. Also, CVD-5i
o. Unlike the case of forming a film, there is no need to provide densification treatment, so the process can be simplified. In addition, the high resistance layer 5 has a resistivity with small variations, so by using this epitaxial uniform, it is possible to easily produce a semiconductor device with high breakdown voltage and excellent device characteristics. Obtainable.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明化係るエピタキシャルウエノ
）の製造方法によれば、低抵抗率の基板上に高抵抗率で
しかも抵抗率のばらつきの小さい高抵抗層を容易に形成
することができる。As explained above, according to the manufacturing method of epitaxial wafer according to the present invention, a high resistance layer having high resistivity and small variation in resistivity can be easily formed on a low resistivity substrate.

その結果、高耐圧を有して素子特性の優れた半導体装置
を容易に製造することができる等顕著な効果を有するも
のである。As a result, it has remarkable effects such as being able to easily manufacture a semiconductor device with high breakdown voltage and excellent device characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第５図は、本発明に係るエピタキシャルウェ
ハの製造方法を工程順に示す説明図である。 １・・・基１ｆｌ、１ｍ・・・基板表面、２・・・多結
晶シリコン膜、１・・・ウェハ、４・・・酸化膜、５・
・・高抵抗層、故・・・エピタキシャルウェハ。 第１１１ 第２図 第３ＷＪ 第４図 第５図 璋FIGS. 1 to 5 are explanatory diagrams showing the method for manufacturing an epitaxial wafer according to the present invention in order of steps. DESCRIPTION OF SYMBOLS 1... Base 1fl, 1m... Substrate surface, 2... Polycrystalline silicon film, 1... Wafer, 4... Oxide film, 5...
...High resistance layer, therefore...epitaxial wafer. 111 Figure 2 Figure 3 WJ Figure 4 Figure 5 Zhang

Claims (1)

【特許請求の範囲】[Claims] シリコン基板の表裏面に多結晶シリコン膜を堆積する１
寝と、該多結晶シリコン膜の表面に酸化膜を形成する工
程と、前記基板の表向ＩたはＪｊｌｌが露出するように
片面儒の該酸化膜及び前記多結晶シリコン膜を除去する
工程と、残存した他ｍ＊の該酸化膜及び前記多結晶シリ
コン膜を保ＩＩＩＩＩＩｉとして、露出された前記基板
上に高抵抗層を形成する工程とを具備することを％像ト
スるエピタキシャルウェハの製造方法０Depositing polycrystalline silicon films on the front and back surfaces of a silicon substrate 1
a step of forming an oxide film on the surface of the polycrystalline silicon film; and a step of removing the oxide film and the polycrystalline silicon film on one side so that the surface I or Jjll of the substrate is exposed. , a step of forming a high resistance layer on the exposed substrate while preserving the remaining oxide film and the polycrystalline silicon film. 0
JP7943282A 1982-05-12 1982-05-12 Preparation of epitaxial wafer Pending JPS58197723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7943282A JPS58197723A (en) 1982-05-12 1982-05-12 Preparation of epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7943282A JPS58197723A (en) 1982-05-12 1982-05-12 Preparation of epitaxial wafer

Publications (1)

Publication Number Publication Date
JPS58197723A true JPS58197723A (en) 1983-11-17

Family

ID=13689711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7943282A Pending JPS58197723A (en) 1982-05-12 1982-05-12 Preparation of epitaxial wafer

Country Status (1)

Country Link
JP (1) JPS58197723A (en)

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