JP2733975B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a semiconductor substrate in which a silicon epitaxial film is formed on a P ⁺ substrate containing boron at a high concentration.

[Conventional technology]

Conventionally, an epitaxial wafer formed by forming an epitaxial film 22 on a P ⁺ substrate 21 as shown in FIG. 7 is effective for preventing latch-up between elements and α-ray soft error. It is used for circuit elements and ultra-high-speed storage circuit elements. At this time, it is effective for the P ⁺ substrate to contain as high a concentration of boron as possible and to have a low resistance in order to prevent latch-up and to prevent α-ray soft errors. Further, since a silicon epitaxial film formed on a P ⁺ substrate is a device formation region, an epitaxial film having a resistivity approximately two orders of magnitude higher than that of a P ⁺ substrate is used in practice. However, the lattice constant of a P ⁺ substrate containing boron decreases as the boron concentration increases, and when the resistance is reduced, the difference between the lattice constant and the epitaxial film becomes large, causing large warpage and misfit dislocation of the wafer. For this reason, a conventional semiconductor device using this type of epitaxial wafer has used an epitaxial wafer in which the content of the boron concentration is suppressed in order to prevent warpage and misfit dislocation of the wafer. In addition, such an epitaxial wafer causes heavy metal gettering by damaging the back surface by sandblasting. In this gettering method, particles (particles) are generated from the back surface during the device forming process.

[Problems to be solved by the invention]

Since the semiconductor device using the conventional silicon epitaxial wafer described above can not be sufficiently reduce the resistance of the P ⁺ substrate since suppressed to the extent that Misufuitto dislocation does not generate boron content of P ⁺ substrate, latchup, alpha ray soft There is a drawback that sufficient measures for improving device characteristics such as error prevention measures cannot be taken.

Further, the P ⁺ substrate has a disadvantage that excessive oxygen precipitation defects occur because the boron concentration is within a range in which the boron concentration suppresses the warpage of the wafer and the occurrence of misfit dislocations.

Furthermore, in the gettering method by sandblasting, which has conventionally been used for epitaxial wafers, particles are generated during a device forming process, and these cause device failure.

[Means for solving the problem]

The semiconductor device of the present invention uses a semiconductor substrate in which an epitaxial film having a resistivity higher than that of the P ⁺ substrate by two digits or more is formed on both surfaces of a P ⁺ substrate containing boron at a high concentration,
It has misfit dislocations based on the difference in lattice constant between the P ⁺ substrate and the epitaxial film.

The present inventor has Misufuitto dislocations generated in a silicon epitaxial wafer with the P ⁺ substrate is formed in a P ⁺ substrate in the vicinity of the interface between the epitaxial film and the P ⁺ substrate, the dislocation generated in the LOCOS ends, etc. Have greatly different properties, and have found that they do not protrude to the surface even after the subsequent heat treatment step and have no adverse effect on devices formed on the epitaxial film.

Conversely, they have found that this misfit dislocation has a strong gettering effect of capturing contamination such as heavy metal elements that enter during the device manufacturing process.

The semiconductor device including the misfit dislocation of the present invention is invented on the basis of the above-described discovery made by the present inventor, and basically reviews the idea that the conventional misfit dislocation has an adverse effect on the device to reduce the misfit dislocation. It is intended to reduce the resistance of the P ⁺ substrate by actively incorporating it. In particular, using the semiconductor device of the present invention.
The P ⁺ substrate has misfit dislocations on both sides or the back side.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a semiconductor substrate used in one embodiment of the present invention. FIGS. 2 (a) to 2 (d) show a manufacturing method according to an embodiment of the present invention, having a silicon epitaxial film 1,5 and a misfit dislocation generation region 2,4 on both surfaces of a P ⁺ substrate 3. FIGS. It is a board | substrate longitudinal cross-sectional view. First, a silicon dioxide film 7 was deposited to a thickness of 5000 ° on the surface of a P ⁺ (100) substrate 6 having a diameter of 6 inches and a specific resistance of 0.005 Ω · cm (FIG. 2A). An ordinary chemical vapor deposition (CVD) method was used as a deposition method. Next, as shown in FIG. 2B, a silicon epitaxial film 8 was grown to a thickness of 15 μm on the back side of the P ⁺ substrate 6. In epitaxial growth, the growth temperature is 1150 ℃,
At normal pressure, a mixed gas of silicon tetrachloride (SiCl ₄ ) and hydrogen (H ₂ ) was used as a supply gas. Next, the silicon dioxide film 7 on the surface was removed with a hydrogen fluoride solution (FIG. 2C).
Finally, a silicon epitaxial film 11 is formed on the surface side of the P ⁺ substrate 6.
Was grown to a thickness of 10 μm to obtain a silicon epitaxial wafer as shown in FIGS. 1 and 2 (d). In the epitaxial growth, the growth temperature is 1150 ° C., normal pressure, and silicon tetrachloride (SiCl ₄ ) and hydrogen (H
₂ ) A mixed gas of diborane (B ₂ H ₆ ) was used. On this occasion,
The specific resistance of the silicon epitaxial film 11 was adjusted to 10 Ω · cm by adjusting the amount of diborane.

After cleaving the wafer, the wafer was etched with a defect selective etchant to evaluate the occurrence of misfit dislocations. As a result, as shown in FIG.
It was confirmed that 4 was formed.

As a reference sample, 6 inch, specific resistance 0.005Ωcm
By growing a silicon epitaxial film 22 to a thickness of 10 μm on a 0.02 Ω · cm P ⁺ (100) substrate 21 in the same manner as in this embodiment, a silicon epitaxial wafer having a conventional structure as shown in FIG. Obtained.

Using the above three types of silicon epitaxial wafers, a 1-Mbit dynamic random access memory device (hereinafter referred to as 1MDRAM device) was prepared, and the warpage of the wafer, the amount of particles generated from the back surface, and the device yield were compared. 1 The amount of warpage of the wafer before the formation of the MDRAM element is -25 μm for the silicon epitaxial wafer of the present invention (positive when the wafer surface side is convex), and for the conventional silicon epitaxial wafer, the P ⁺ substrate specific resistance is 0.005Ω.
・ Cm: 50μm, P ⁺ substrate specific resistance: 0.02Ω ・ cm: 10
μm (FIG. 3). The warpage of the wafer after the formation of the 1MDRAM element is 20 μm for the silicon epitaxial wafer of the present invention, and 95 μm for P ⁺ substrate specific resistance of 0.005 Ωcm for the silicon epitaxial wafer of the conventional structure.
⁺ 60 μm with a substrate specific resistance of 0.02 Ωcm (No. 3
Figure). Thus, it can be seen that the silicon epitaxial wafer of the present invention does not cause a large warpage of the wafer in the 1MDRAM element forming step. In addition, the generation of particles from the back surface was observed in the silicon epitaxial wafer of the conventional structure because the back surface was damaged by sandblasting, whereas the generation of particles was observed.
In the silicon epitaxial wafer of the present invention, since the epitaxial film 1 was provided on the back surface, generation of particles was not observed. Further, the yield of 1MDRAM device was obtained by using the silicon epitaxial wafer of the present invention.
1 The MDRAMB element uses 30% of the conventional structure of a silicon epitaxial wafer with a P ⁺ substrate specific resistance of 0.005 Ωcm, and uses the conventional structure of a silicon epitaxial wafer with a P ⁺ substrate specific resistance of 0.02 Ωcm. 25% improvement compared to This is due to the latch-up due to the low resistance of the P ⁺ substrate,
In order to improve the α-ray soft error resistance and gettering ability, and to prevent the generation of particles from the back surface during the device forming process due to the mirror surface of the back surface, the reduction in yield due to the influence of particles has been suppressed. It is considered that this is because the generation of defects due to thermal stress in the device forming process was reduced by reducing the amount of warpage, and the yield was reduced due to the warpage in the photolithographic process.

Next, as another embodiment of the present invention, an example of a device in which an active region of an element (device) is formed on a P ⁺ substrate will be described. FIG. 4 is a vertical sectional view of a semiconductor substrate used in the embodiment. Silicon epitaxial films 12,1 on both sides of P ⁺ substrate 14
5 and a misfit dislocation generation region 13 on only one side
have. 5 (a) to 5 (d) are vertical cross-sectional views of a substrate showing the manufacturing method of this embodiment. First, a silicon dioxide film 17 was deposited on a surface of a P ⁺ (100) substrate 16 having a diameter of 4 inches and a specific resistance of 0.004 Ω · cm to a thickness of 5000 ° (FIG. 5 (a)). Conventional chemical vapor deposition (CV)
The D) method was used. Next, as shown in FIG. 5 (b), a silicon epitaxial film 18 was grown to a thickness of 7 μm on the back side of the P ⁺ substrate 16. In epitaxial growth, the growth temperature is 11
00 ° C, Pressure 50 Torr, Dichlorosilane (SiH
A mixed gas of ₂ Cl ₂ ) and hydrogen (H ₂ ) was used. Next, the silicon dioxide film 17 on the surface was removed with a hydrogen fluoride solution (fifth step).
Figure (c). Finally, a silicon epitaxial film 20 as shown in FIGS. 4 and 5 (d) was obtained by growing a silicon epitaxial film 20 to a thickness of 2.5 μm on the surface side of the P ⁺ substrate 16. In the epitaxial growth, a growth temperature of 1100 ° C., a pressure of 50 Torr, and a mixed gas of dichlorosilane (SiH ₂ Cl ₂ ), hydrogen (H ₂ ), and diborane (B ₂ H ₆ ) were used as a supply gas. The specific resistance of the silicon epitaxial film 20 was adjusted to 2 Ω · cm by adjusting the amount of diborane. After the silicon epitaxial wafer was cleaved, it was etched with a defect selective etching solution to evaluate the occurrence of misfit dislocations. As a result, it was confirmed that the misfit dislocation generation region 13 as shown in FIG. 4 was formed. Also,
As a reference sample, 4 inches, specific resistance 0.004Ωcm and 0.015
By growing a silicon epitaxial film 22 to a thickness of 2.5 μm on a P ⁺ (100) substrate 21 of Ω · cm in the same manner as in the embodiment, a silicon epitaxial wafer having a conventional structure as shown in FIG. 7 is obtained. Was.

Using the above three types of silicon epitaxial wafers
A 1 Mbit dynamic random access memory device (hereinafter referred to as a trench capacitor 1MDRAM) having a structure in which a trench capacitor was formed in a P ⁺ substrate was fabricated, and the warpage of the wafer and the yield of the device were compared. Trench capacitor 1M
The amount of warpage of the wafer before the formation of the DRAM element was −15 μm in the silicon epitaxial wafer of the present embodiment, and the P ⁺ substrate specific resistance was 0 in the conventional silicon epitaxial wafer.
The thickness was 45 μm for 004 Ω · cm and 3 μm for P ⁺ substrate specific resistance 0.015 Ω · cm (FIG. 6). The warpage of the wafer after trench capacitor 1MDRAM element formation, the silicon epitaxial wafer of the present invention, 18 [mu] m, the silicon epitaxial wafer having a conventional structure, P ⁺ substrate resistivity 0.
The thickness was 75 μm for 004 Ω · cm and 40 μm for P ⁺ substrate specific resistance 0.015 Ω · cm. As described above, the warpage of the silicon epitaxial wafer of the present embodiment is caused by the trench capacitor 1M.
It can be seen that large warpage of the wafer does not occur in the DRAM element forming process. In addition, generation of particles from the back surface was observed in the silicon epitaxial wafer of the conventional structure, whereas generation of particles was not observed in the silicon epitaxial wafer of the present invention. Again, the yield of the trench capacitor 1MDRAMB device is 35% lower than that of the 1MDRAM device using the silicon epitaxial wafer of the present invention, compared with the one using the conventional silicon epitaxial wafer having a P ⁺ substrate specific resistance of 0.004Ωcm. ⁺ Compared to that using a conventional silicon epitaxial wafer with a substrate specific resistance of 0.015Ωcm
Improved by more than 30%.

〔The invention's effect〕

Above-described manner, the present invention is, mistakes P ⁺ has both sides P ⁺ 2 digits or more high resistivity silicon epitaxial film from the substrate of the substrate, and caused by a difference in lattice constant between the P ⁺ substrate and the silicon epitaxial layer By forming a device on a silicon epitaxial wafer having a fit dislocation, sufficient latch-up and α-ray soft error resistance were obtained, and the device yield was able to be higher than that of the conventional technology.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor device substrate for explaining one embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are vertical sectional views of a substrate showing manufacturing steps in one embodiment of the present invention. FIG. 3 is a view showing one example of the warpage of a conventional wafer of the present invention in one embodiment of the present invention, and FIG. 4 is a longitudinal section of a semiconductor device substrate for explaining another embodiment of the present invention. 5 (a) to 5 (d) are longitudinal sectional views of a substrate showing a manufacturing process in another embodiment of the present invention, and FIG. 6 is a wafer of the present invention and a prior art in another embodiment of the present invention. FIG. 7 is a longitudinal sectional view of a semiconductor device substrate according to the prior art. 1,5,8,11,12,15,18,20,22 …… Silicon epitaxial film, 2,4,9,10,13,19 …… Misfit dislocation generation region, 3,
6,14,16,21 ... P ⁺ substrate, 7,17 ... Silicon dioxide film.

Claims (1)

(57) [Claims] A silicon epitaxial film having a resistivity higher than that of the p-type silicon substrate by two digits or more on one main surface and another main surface of the p-type silicon substrate to which boron is added as an impurity element; In a semiconductor device having a semiconductor element formed on one main surface of a type silicon substrate, at least one main surface of the P type silicon substrate has a misfit dislocation generation region.