JPS58192431A - Phase comparison protecting relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog type protection relay, particularly to a phase comparison type protection relay. Furthermore, in detail, the present invention allows for automatic online inspection by itself, and can be easily implemented into a semiconductor integrated circuit (IC or LSI), thus reducing the need for small size, high reliability, and low The present invention relates to a phase comparison type image relay that can be easily realized at low cost.

The conventional analog type imager 1111J does not have an automatic inspection function by itself. Therefore, in order to achieve high reliability, automatic inspections are performed on the entire device or system.

The scale of the circuit for automatic inspection is 25 to 30% larger than that of the protective relay device. Therefore, if an attempt is made to achieve even higher reliability, the device becomes larger and larger and the cost increases.

Furthermore, since there is a possibility that the automatic inspection device itself may fail, it is not necessarily sufficient to achieve high reliability.

In addition, in the conventional inspection method, the function of the eyelid protection relay was stopped before inspection was carried out, which had the disadvantage of delaying operation if an accident occurred during the inspection.

The purpose of the present invention is to overcome the above-mentioned conventional drawbacks and to provide itself with an online automatic inspection function.
An object of the present invention is to provide a maintenance relay that is highly reliable and suitable for use in semiconductor highly integrated circuits (LSI).

The present invention focuses on the fact that the direct phase comparison type protection relay does not have a memory element, and has developed an online automatic inspection system that is consistent from input to output without stopping the relay function or affecting the relay characteristics. This makes it possible to check the operation side of rotation.

In other words, the operating time of the maintenance relay is currently 10
~30 msec, and the allowable error is approximately 0.5 msec. Therefore, if automatic inspection can be performed in a time of 0.5 msec or less, online inspection will be possible without affecting the relay function at all.

To this end, in the present invention, the input signal to the relay is switched from the grid voltage and current signal to a DC inspection signal to operate the analog part of the relay within the above-mentioned time range that does not affect the relay function. At the same time, a counter in the phase determination circuit is preset to a value 6ζ that can be counted up sufficiently within the inspection time, and the output time for the inspection signal is counted and the value is determined.

In addition, the present invention takes into consideration the high integration of semiconductors (LSI), and only adds a simple check signal generation circuit, a digital output judgment circuit that can be highly integrated, and a check timing generation circuit, and from the input. This allows for consistent inspection of output.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall circuit configuration to which the present invention is applied.

In the figure, 1 is a group of analog switches for switching between input voltage and inspection signals, and 2 is an inspection signal generation circuit, which will be described later. Further, numeral 3 is a setting circuit, and in this embodiment, since a phase comparison type reactance relay is used as an example of the protection relay, this is a coefficient setting circuit.

4 is a vector synthesis (addition) amplifier circuit, 5 is an amplifier circuit, 6
and 7 are square wave conversion circuits (
comparator).

Further, 8 is a phase determination circuit for the outputs of the square wave conversion circuits 6 and 7, 9 is an output check circuit for the inspection signal (voltage), and 10 is an inspection command, a clock signal for output determination control or phase determination for the inspection signal, etc. This is a timing generation control circuit that emits.

The operation of the present invention will be explained in detail below using FIGS. 2 to 5.
IIIC Explain.

First, with reference to FIG. 2, the relationship between the input signal and the inspection signal will be explained.

2 shows an example of the output waveform of the vector synthesis circuit 4 of FIG. 1 when the current I and the current I are selected by the analog switch group 1.

In addition, (N part and +81 part are inspection signals (voltage) described later.
Give an example.

The dotted line (iz) in (2) in the figure indicates the input current I in Figure 1.
2 shows an example of the output waveform of the amplifier circuit 5. In addition, the Δ portion in (2) above and (B) s+t, and an example of generation of an inspection signal, which will be described later, are shown.

(3) in Figure 2 shows the waveform of (iゑ-*) in (1) above when it is binarized with 10 as the threshold voltage, as shown in (1). The output of the square wave conversion circuit 6 is shown in FIG.

(4) in the figure shows the waveform of (IZ) in (2) above, (
2) shows the output of the square wave conversion circuit 7 in FIG. 1 when it is binarized as a +ctl threshold voltage.

(5) in FIG. 2 shows an example of AND (logical product) output of stop waves of a known reactance relay. In this example, the AND output is always "O". In other words, the relay output is not emitted (reactor relay, as is known, operates when the overlap angle is 90° or more)
.

(6) in Figure 2 is the AND output of the waveform cap and cap' for the inspection data of (1) and (2) above, and (7) is the AND output of the (chain part) of (1) above, similar to (6). AND of (B)' in (2)
Show the output.

That is, the present invention switches the input voltage and outputs the check signal (
As described above, a direct current voltage (with which the AND condition is satisfied for both positive waves and negative waves) is applied to the protective relay for a very short period of time to self-inspect the protective relay.

Next, a method for switching input voltage and inspection signal (voltage) will be described with reference to Fig. 3.4. The reference numeral 1 in FIG. 3 indicates the same analog switch group as the reference numeral 1 in FIG. Further, (A) and (# in these figures are control signals for switching input voltages 1 and 2 to inspection signal voltages).

Regarding the timing of the control signal, (1) and (2) in FIG.
). In other words, when the control signal (a) is level,
When the input voltages 1 and 2 are selected, on the other hand, when the control signal (b) is level, the check voltage is selected. In other words, the analog switch group 1 switches the inspection voltage and the input voltage in a time-sharing cyclic manner every period T, and supplies the same to the subsequent circuit.

As can be seen from the above explanation, the inspection time a in Figure 4
and β correspond to (4) (Ar(Bl and (w) part in FIG. 2, and the inspection data shown in FIG. 2 is generated during these a and β times. The inspection cycle T corresponds to the inspection cycle T shown in (1) of FIG.

The inspection times Q and β and the inspection period T may be arbitrarily controlled by the timing generation control circuit 10 shown in FIG. However, it goes without saying that this inspection time, β, is a time that does not affect the relay characteristics (in terms of order, it is less than 1 mj). Further, the inspection period T may also be arbitrarily determined. In this example, 1 cycle per cycle.
An example of performing multiple inspections is shown.

Next, a method of inspecting the inspection voltage in the phase determination circuit 8 will be explained using FIG. In FIG. 5, each reference numeral 6, 7, 8.9 and 10 indicates the same thing as in FIG.

In the phase determination circuit 8, new elements were added for the purpose of the present invention (AND gates 14, 15, 19°, 20.
These are a constant setting circuit 21, an AND gate 27 and 28, and an OR gate 29, and the stiff parts are not shown by thick lines. The other blocks are exactly the same as the known conventional configuration.

That is, in the figure, 11.12 is an AND gate, 1
3 is a NOR gate, 16 to 18 are phase determination counters,
22 is an OR gate, 23 and 24 are 7 lip flops, 25 is an OR gate, and 26 is a block gate.

First, as the inspection signal (voltage), (1) and (
An example will be described in which ``Ki'' and ``Do'' are applied, which is not shown in 2).

The stiffness check voltage is logically multiplied by an AND (logical product) gate 11 in FIG. An example of the output in this case is shown in (6) of FIG.

At this time, this inspection voltage is set to a constant based on the condition that (4) both circles are Lebel and the inspection command signal (one output of the ANDNO gate) that indicates that the inspection is in progress and is given via the signal line a. The value of the circuit 19 is transferred to the counter 16
Preset to .

Then, the duration of the output voltage (output of the gate 14) is counted by the counter stepping clock applied via the signal line. A flip-flop 23 is set by the count-up signal from the counter 16.

The ANDNO gate and 28 are gates for inhibiting the output generated by the inspection, and the signal 1
The output of the OR gate 25 and the ANDNO gate is inhibited by a signal applied via the ° branch line C (only at the time of one inspection).

Judgment regarding the check signal is performed by determining in the output check circuit 9 whether a predetermined output width is obtained for a predetermined check signal (voltage). The result is then output to the outside via the signal line d.

As described above, the signal line e transmits a command to reset the 7 ribs 70 tabs 23 and 24, which were forcibly set by the inspection signal, at the same time as the inspection is completed.

Further, the signal line f is for transmitting a signal corresponding to the input switching signal (a) and tc4 in FIGS. 3 and 4.

Note that this signal should be inhibited when the gate 25 or 26 is outputting a level when the inspection is not in progress (in steady state), that is, when the video relay is operating. be. That is, the inspection according to the present invention is automatically performed only when the relay is not operating.

In the case of a negative voltage check signal such as (Bl, (B') in (1) and (2) in FIG. 2, the ANDNO gate in FIG. 5.

It can be easily inferred that the paths of the counter 18 and the flip 70 knob 24 can be checked in the same manner as described above.

That is, the present invention presets a scheduled value in the phase determination counter at the time of inspection, thereby shortening the number of counts during normal relay operation (normally equivalent to 5 mm seconds), and improving the operation of the phase determination section. for a very short time (for example, 0.5
It is designed to allow inspection in less than milliseconds).

Next, inspection of the paths of the NOR gate 13, counter 17, and OR gate 22 will be described.

The output of NOR gate 13 is AND gate 11 and 1
When the two outputs are both at the θ level, that is, when the relay is not operating, the level is level. The duration of this level output is counted by a counter 17. This is a constant movement.

That is, normally, the duration of the level output from the NOR gate 13 is counted, and when the duration of the level output exceeds a certain value (when the relay is not operating), the counter 17 is incremented, and the OR gate 22 is incremented. Through this, the flip-flops 23 and 24 are reset at a certain period (the count-up repetition period of the counter).

At the time of inspection, the constant set in the constant setting circuit 20 similar to 19 and 21 above is set by the signal line g (the timing will be described later) (in a short period of time, the counter 17 is counted up). The counter 17 is preset or loaded and is incremented by a counter increment pulse (given via a signal line).

Then, the count up signal (output of 17) is applied to the flip 70 knobs 23 and 24 via the OR gate 22,
Reset Kowara no Flip 70 Tsubu. Zarani, O
The outputs of the R gate 25 and the AND gate 26 are introduced into the tick circuit 9 via the OR gate 29, where the
This is to check that the lip-flops 23 and 24 have failed to be reset.

FIG. 6 is a block diagram showing detailed circuits of the output check circuit 9 and timing generation control circuit 10 in FIG. 5. Further, FIG. 7 is a waveform diagram showing an example of the timing of the control signals a to h generated by each of the circuits 9 and 10 and the outputs of the flip-flops 23 and 24.

In FIG. 6, 91 in the output check circuit 9 is a counter for checking whether a predetermined inspection output is obtained after a certain period of time from the inspection command, and 92 is for counting a certain period of time (for example, inspection time). 93 is an inverter gate,
Reference numeral 94 indicates an OR gate, and reference numeral 95 indicates an AND gate.

At the time of inspection, the constant counter 91 of the constant setting circuit 92 is loaded by the signal (a) on the signal line f whose timing is shown in FIG. start.

If the circuit is normal, as shown in Figure 7,
The outputs of the 7-lip flops 23 and 24 in Fig. 5 (
F/F output) becomes a level after inspection time A.

As is clear from FIGS. 5 and 6, this output is input to the inverter 93 in FIG. 6 via the OR gate 25, AND gate 26, and OR gate 29 in FIG. Before doing so, the counter 9
It acts to reset 1.

Therefore, it goes without saying that the constant of the counter preset constant setting circuit 92 is set to a value that is smaller than the time A.

When the circuit becomes abnormal, the output of the OR gate 29 is not generated at a predetermined time, so the counter 91 counts up. Therefore, by monitoring the output of this counter 91, the quality of the inspection results can be checked.

Further, the counter 17 shown in FIG. 5 is inspected as follows.

The value of the constant setting circuit 20 is loaded or preset into the counter 17 by the signal on the signal line g shown in FIG. 7, and counting is performed during the period when the signal g is at the level. When this counter 17 counts up, as shown in FIG.
24 is reset and its output becomes the θ level.

Therefore, as shown in FIG. 6, the output of the stiff 7-lip flop (actually, the output signal is applied to the AND gate 95 via the OR gates 25 and 29);
Figure 7: AND with the timing pulse h shown in Figure 1
By taking the signal using the ND gate 95, it is possible to check the quality of the counter 17.

That is, the counter 17 is operating normally, so to speak.
No level signal is generated on the signal line d connected to the output of the R gate 94. On the other hand, if the seven rib flops 23 and 24 are not reset, a rubel signal appears on the signal line d during the rubel period of the signal line. Therefore, the quality of the counter 17 can be checked by monitoring the signal level of the signal line d.

Above, we have explained the operation during inspection, but finally,
The timing of the signals on each signal line will be briefly described in detail using FIG.

Signal line a; a in FIG. 7 shows the timing of the signal on signal line a in FIGS. 5 and 6, A is the inspection time, Tn.

T (leaf l), ... - ... indicate the inspection cycle.

Signal line b; b in FIG. 7 shows the timing of the signals on the signal lines in FIGS. 5 and 6. This signal is a clock pulse for incrementing the counter.

Signal line C; Similarly, signal line C is for relay output locking, and is for locking the relay output (output of gates 25 and 26 in FIG. 5) during the θ level period.

Signal line d; d in FIG. 7 shows the state of signal line d. That is,
When the A period inspection was carried out in the T(n++) period, the fifth
The figure shows the timing when the flip-flop 23 or 24 is not set and the counter 91 in FIG. 6 counts up to notify an abnormality.

Signal line e: The signal line e is used for inspection as shown in Figure 5.
Flip-flops 23 and 24 set to i,
This is an example of timing when resetting unconditionally.

Signal line f: The signal line f carries the signals (1) and (2) shown in FIG.
B) and (C4).

Signal line g; Signal line g is a signal line for transmitting a signal for checking the counter 17 in FIG. While this upper signal is at the level, the counter 17 increments, and when the counter 17 counts up, the outputs of the flip-flops 23 and 24 (FIG. 5) are reset.

Signal line h: The signal line is the Lebel timing note above it, and is used to transmit a timing pulse to check whether the output of the flip 70 knob 23 or 24 is at the 0 level. That is, the flip-flop 23
and 24 indicate timing pulses for checking whether or not it has been set by inspection and reset by inspection.

Finally, the T(n+J phase in FIG. 7 is the flip 70
This shows an example of the waveform when the outputs of the knobs 23 and 24 are already in the level and the relay is in operation.

At this time, when the child is one year old, the relay output (signal passed through the OR gates 25 and 29 from the outputs of the flip 70 knobs 23 and 24) is sent to the basic timing generator 101 shown in FIG.
By inputting through the signal line it, control is performed so that timing related to inspection does not occur.

Although the specific circuit configuration for such control is not shown, each signal line is controlled by the relay output signal (for example, A
It is easy to guess that it can be implemented by simply taking the ND condition.

In addition, the inspection signals (1) and (2) in Figure 2, (A
)'(Bl and (BY amplitude) are shown in Figure 2 (6
) and (7), any value that satisfies the AND conditions may be used, and it goes without saying that the inspection time and period may be set arbitrarily.

Finally, the positive and negative check signal (voltage) generation circuit will be described using FIGS. 8 to 10. FIG. 8 shows a specific example of the circuit, and FIG. 9 shows the waveforms of each part thereof. In addition, FIGS. 10(IL) to (e) indicate each operation time TD(,N-
1), TA(N), TB(N).

9 is a schematic circuit diagram for explaining the connection state of the circuit of FIG. 8 at TC(N) and TD(N). FIG.

Waveform 1f) (2) 1 in Figure 9, (1) and f in Figure 2
21c! Inspection signal (4) (shows exactly the same timing as Bl). Roughly speaking, waveforms (4) to (8) are for the switches SWI and SW2.

The timing of the control signals of SW3, SW4, and SW5 (the switch for the cough guard does not close when the cough is on) is shown fidgetingly.

The operation of the inspection data generation circuit shown in FIG. 8 in each time period is as follows.

1) During the operation time of TA(N), switch SW3
゜Turn on SW4, and the voltage (positive voltage) that is not charged to the capacitor C is generated from the operational amplifier OP as the inspection signal data). This inspection signal has the waveform (
It is output at time a shown in 2).

11) At the operating time of TB(N), switch SWI
.

Turn on SW4 to charge the capacitor Ct to a constant voltage.

1it) In the operating time of TC(N), switch SW
2°SW5 is turned ON, and the voltage (positive voltage) that is not charged in the capacitor C is generated from the operational amplifier OP as a negative polarity check signal (data). This inspection signal is output at time β shown in waveform (2) in FIG.

IV) At the operating time of TD(N), switch SWI
, ! Turn on SW4 to charge capacitor C with a constant voltage.

The above operations are repeated. Further, as shown in FIG. 8, the output voltage at this time is divided into appropriate magnitudes using a voltage dividing resistor or the like, and outputted as inspection signals (il and (v)).

For example, as shown in the figure, the output of the operational amplifier OP can be used as is (i) in Figure 1, or the output after being voltage-divided by resistance (
If vl is given as tv+ in Fig. 1, a voltage (vl) is applied to the coefficient setting circuit 3, and an in-phase voltage (inspection signal) of +11 is applied to the vector synthesis amplifier circuit 4 and the amplifier circuit 5. .

Therefore, the vector synthesis amplification circuit 4 performs the calculation of (iv) instead of the calculation of (iz-*), and the amplifier circuit 5 performs the amplification of +11 instead of the amplification of IZ.

Since the voltages across the two sides are in phase, it is easy to understand that the logical product is established as described above.

According to the present invention, inspection of the protection relay can be carried out online without stopping the function of the relay and without affecting the relay characteristics.
[can be achieved.

Further, since only the additional circuits (circuits suitable for single integration (gates, analog switches, operational amplifiers, etc.)) are included, miniaturization can be easily achieved.

Furthermore, by applying the present invention, it is possible to eliminate the conventional automatic inspection of the entire device (for example, once a day). As a result, it is expected that the protection relay device will have higher reliability, be significantly smaller in size, and lower in cost.

[Brief explanation of drawings]

Figure f41 is a block configuration diagram of one embodiment of a typical protective relay (reactance relay) to which the present invention is applied, Figure 2 is a waveform diagram showing the relationship between the inspection voltage and input voltage of the present invention, and Figure 3 is the input voltage. Components of the changeover switch, FIG. 4 is a waveform diagram showing the control timing of FIG. 3, FIG. 5 is a detailed block diagram of the phase determination circuit, FIG. 6 is a detailed block diagram of the output check circuit and timing generation control circuit, Fig. 7 is a waveform diagram showing an example of the timing of each control signal, Fig. 8 is a diagram showing an example of the inspection data generation circuit, Fig. 9 is an operation waveform diagram thereof, and Fig. 10 is a diagram showing the wiring state in each case. It is. l...Analog switch group, 2...Inspection signal generation circuit, 3...Coefficient setting circuit, 4...Vector synthesis (addition) circuit, 5...Amplification circuit, 6, 7...Square Wave conversion circuit (comparator), 8... Phase determination circuit, 9...
- Output check circuit, 10... Timing generation control circuit, 16-18... Phase determination counter, 19-
21...constant setting circuit representative patent attorney Michihito Hiraki 27-23 Figure Q Yao 6 Figure 27 Figure 28 Figure 9 Figure 10 Figure

Claims (4)

[Claims] (1) A settling circuit and a vector synthesis circuit that are supplied with signals such as system voltage and current, a square wave conversion circuit that shapes the outputs of both circuits, and a judgment output based on the output of each square wave conversion circuit. a logic circuit that is supplied with the output of the square wave conversion circuit and performs a logical operation; a counter that counts the output $414 of the logic circuit; Generates an inspection command signal indicating that an inspection is being carried out in the phase comparison type image M, IJ, which is composed of means for supplying tarock pulses to a counter and means for generating a judgment output based on the counting result of the counter. Means and inspection signal (pressure)
means for switching the input to the settling circuit and the vector synthesis circuit from a signal such as a pressure current of the system to the inspection signal (voltage); and a constant setting circuit provided corresponding to the counter. , means for presetting a constant of a corresponding constant setting circuit in the counter based on a logical product of a logical operation of the inspection signal (pressure) in the logic circuit and an inspection command signal; An output check circuit that determines the quality of the output depending on whether it is generated at a predetermined time, and a gate that prohibits the determination output from being transmitted to the outside while the inspection command signal is being generated. A phase comparison type protective relay characterized by the following: (2) The phase comparison type image dIJ-ray according to claim 1, wherein positive voltage and negative voltage are alternately generated as the inspection signal (voltage). (3) The phase comparison image M IJ according to paragraphs 1 and 2 of the claims, characterized in that the generation of the inspection signal (voltage) is carried out time-divisionally and periodically. −〇 (4) Means for prohibiting the supply of the inspection command signal while the judgment output based on signals such as system voltage and current indicates that the train is about to depart. The double-comparison image-peak relay described in Izuka of Section 3.