JPS58191525A - Tap selecting circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of disable operation against multiple selection and non-selection of a tap, by forming the circuit in such a way that an input is not given to an operation circuit and the operation is performed with a prescribed operation input when the tap selection for plural number of input circuits is done. CONSTITUTION:Input conditions 1a-1c to be preset are selected at taps 2a- 2c and given to AND circuits 5a-5c, and 6a-6c. the circuits 6a-6c produce outputs 7a-7c when two taps among the taps 2a-2c are selected at the same time. The output enters an OR circuit 8, where an output 9 is produced. The output 9 is inverted 10 and becomes an inhibiting condition of the circuits 5a- 5c. Thus, the circuit 5a-5c are made effective only when no output 9 exists and ineffective when the output 9 exists. Further, the output 9 is introduced to an AND circuit 11, which gives the preset operating condition 12 to an operation circuit 3, where the operation is done with the condition 12 and gives an output 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tap selection circuit, and particularly to a tag selection circuit for preventing a plurality of tags from being selected simultaneously.

[Technical background of the invention]

In a tag selection circuit having a plurality of taps, one tap is usually not selected for control or sleep control. ff1J For example, with digital relays, there is a small percentage that various characteristics can be achieved by changing the program on the same hardware, but in order to take advantage of these characteristics, it is necessary to incorporate some possible system requirements in advance. Even if the applicable system conditions change, it can be handled by simply switching the taps without changing the program each time.

Also, even if we consider the case where the power transmission line is 2 terminals or 311I terminals, there are errors in the accumulation of υ per terminal due to minimum sensitivity switching, CTl1l difference, S terminal error, sampling error, etc. If you try to increase the overall sensitivity as much as possible, you will inevitably have to lower the minimum sensitivity in the case of three terminals compared to the case of two terminals. If the same sensitivity is applied to multiple terminals such as 2, 3, or 4 or more terminals, the sensitivity will have to be set to the lowest level, and if there are fewer terminals, the sensitivity will be lower than necessary. . Therefore, it is conceivable to use a switching circuit to select the optimum sensitivity so that the characteristics match the system conditions.

[Problems with background technology]

Here, problems with the conventional tap selection circuit will be explained with reference to FIG. In addition, to simplify the explanation, there are 3 selection taps.
We will explain two cases. 1 a.

lb and le are calculation conditions that are set in advance, and using these, tap 2 m + in the tap and f selection section 2
2 b e 2 e is selected, and one of the arithmetic conditions 1a, lb, le is introduced into the arithmetic circuit 3 to perform a predetermined response and output 4 is derived. Here, 762 m in the f selection section 2.

If either one of 2b or 2e is selected, the arithmetic circuit 3 can respond normally, but if two or more tags wA' are selected, the arithmetic circuit 3 It cannot be determined whether the condition should be used, and an incorrect output or no output is generated at output 4. On the other hand, when none of the taps 2m, 2b, and 2c are selected, no calculation conditions are introduced into the logic circuit 3, so it is impossible to expect a correct output as the output 4.

That is, a plurality of tags may be selected at the same time, or there may be cases where no security tag is selected and used for operation.

[Purpose of the invention]

The present invention has been made for the purpose of solving the above-mentioned problems.It is an object of the present invention to provide a T, f selection circuit in which a necessary tap is correctly selected and a plurality of tags are not selected at the same time. It is an object.

[Summary of the invention]

The present invention provides a logic circuit for each calculation condition circuit that is an input, so that when a plurality of λ power circuits are selected, they are not introduced into the calculation circuit, and in that case, input according to predetermined calculation conditions is provided. is introduced into an arithmetic circuit to be computed.

[Embodiments of the invention]

Embodiments will be described below with reference to the drawings. Figure 2 is an elliptic diagram of the T and F selection circuit according to the present invention. The symbols 4 to 4 correspond to Figure 1 in the figure. 5”t
5b*5e is a circuit inserted into each input condition circuit, and does not generate an output when a plurality of input conditions exist, but generates an output when one input condition exists. 6m, 6b, and 6e are the same L: <' It is an AND circuit, and it is O only when any two input conditions exist.
The output is introduced into the R circuit 7. 10 is a NOT circuit which inverts the output when any two inputs are present, thereby blocking the outputs of the AND circuits 5a, 5b, and 5e. 11
is an AND circuit that derives an output on the condition that any two input conditions exist, and in that case, it is introduced into the arithmetic circuit 3 together with a preset arithmetic condition 12. Therefore, the operation is as follows.

That is, the input conditions 1a and lb are preset.

1c tap selection part 2 cod 762 m, 2 b
, 2e, AND circuits 5a, 5b,
At the same time, another AND circuit 6a, 6b
, 6e. Then, when taps 2a and 2b are selected at the same time, AND circuit 6a traps when taps 2a and 2b are selected at the same time, AND circuit 6a and 2c are selected at the same time. At the same time, output cuffs m, 7b, and 7e are derived, respectively.

These outputs enter an OR circuit 8 and produce an output 9.

The nine outputs of the OR circuit 8 are inverted by the NOT circuit 10 and become prohibition conditions for the AND circuits 5m, 5b, and 5e.

This is valid only when there is no output 9 of the AND circuit 5m, 5b, 5e FiOR circuit 8, and invalid when there is an output 9 of the OR circuit 8. In short, if two or more taps are selected at the same time, taps 2m, 2b, 2e
The selected conditions will not be introduced into the performance circuit 3.

On the other hand, the output 9 of the OR circuit 8 is introduced into the AND circuit 11, and a preset calculation condition 12 is introduced to the calculation a circuit 3. The calculation circuit 3 derives the calculation η[7 output 4 from the calculation condition 12. Here, as the calculation condition 12, any one of the calculation conditions 1a, lb, and lc used in the tap selection section 2 may be used, or another condition may be set.

You can leave it there. In any case, the output 4 of the arithmetic circuit 3 must be selected in such a way that it can provide a safe response.

FIG. 3 is a block diagram of another embodiment of the present invention. Reference numerals 1 to 11 in the figure correspond to those in FIG.

If two or more taps 2'' w 2 b + 2 e are selected at the same time, the respective calculation conditions are not introduced into the calculation circuit 3, as in the case of FIG.

13 is a circuit for storing the calculation conditions immediately before two or more tags are selected; the output 9 of the OR circuit 8, which is generated when two tags are selected at the same time, is used to store the AND circuit 11; is turned on, and the storage condition 13 is set as the calculation condition of the calculation circuit 3.

If a plurality of taps and taps are selected at the same time, the system does not switch to the tap selections unless the old tap selection is canceled.

FIG. 4 is a block diagram of still another embodiment of the present invention.

Reference numerals 1 to 4 in the figure correspond to those in FIG.

14 is an OR circuit, 15 is a NOT circuit, 16 is the output of the NOT circuit, 17 is an AND circuit, and 18 is a preset performance condition. Here, the outputs of the tags 2m, 2b1, and 2c are not directly introduced into the arithmetic circuit 3, but also output from the OR circuit 14.
is input and one of the taps is selected,
Since the output of the OR circuit 14 is generated, the output 16 of the NOT circuit 15 does not exist, and therefore the condition of the AND circuit 17 is also not satisfied. Now, suppose that no tap is selected, there is no output from the OR circuit 14, and the NOT circuit 15
An output 16 is generated. Therefore, the AND condition of the preset performance condition 18 and the output 16 of the NOT circuit 15 is established and is introduced into the arithmetic circuit 3. It is possible to perform calculations based on the calculation conditions 18 that have been set in advance, and no calculations will be performed. The calculation condition 18 is the performance condition 1 m + 1 used in the tap selection section 2.
Either b 11 e may be used.

FIG. 5 is a configuration diagram of still another embodiment according to the present invention. Reference numerals 1 to 4 and 14 to 18 in the figure correspond to those in FIG. Here tag 2a, 2b.

4, the output 16 of the NOT circuit 15 is generated when none of the signals 2c and 2c are selected. 19L
The storage circuit stores calculation conditions before no tags are selected. The calculation condition that is dry is 143
After being selected, the previous calculation condition can be maintained even if the selection of the tag is stopped, since contact failure of the tag that selects the calculation condition is included. In addition, if the calculation conditions have not been inputted to the calculation circuit 3 in advance, the output of the storage circuit 19 is introduced via the NOT circuit 20, and the NOT circuit 15 is informed that no f has been selected. After confirming the output, the preset calculation condition 18 is validated and inputted to the calculation circuit 3. As a result, the calculation circuit 3 can perform calculation according to the calculation condition 18 and derive the output 4.

By the above method, calculation settings can be made when multiple taps and f are selected and when no tap is selected. Also, when monitoring the selection status of these taps,
Output 9 of the OR circuit 8 of FIGS. 2 and 3, and FIG. 4.

The output 16 of the NOT circuit 15 shown in FIG. 5 is constantly monitored, and if these outputs continue for a certain period of time, it is possible to issue an alarm by some method to call attention. Although the number of 7Ps is set to three for ease of explanation, it is needless to say that the present invention is not limited to the above explanation and can be applied to any device having a plurality of taps.

〔Effect of the invention〕

As explained above, according to the present invention, a logic circuit is provided in each of the arithmetic condition circuits, and a plurality of input circuits among them are
When a selection is made, no input is introduced into the arithmetic circuit, and the arithmetic operation is performed using a predetermined arithmetic input, so it is possible to prevent the operation from being impossible due to multiple selections of E and D and no selection. It is possible to provide a data selection circuit that can prevent such problems, and at the same time, can take prompt action by issuing an alarm.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining a conventional tap selection circuit, and FIG. 2 is a configuration diagram of an embodiment of a tag selection circuit according to the present invention, #c3
The figure shows the configuration of another embodiment, FIG. 4 shows the configuration of still another embodiment, and FIG. 5 shows the configuration of still another embodiment. 1 m + 1 b, 1 e, 12.18...Calculation condition 2...Tap selection section 2m, 2b, 2a...
・Tap 3...Arithmetic circuit 4...Arithmetic circuit output 5m, 5b, 5e, 6m+6b, 6etll+17
, 21... AG circuit 7mv7b, 7e - - AND circuit output 8.14... OR circuit 9... OR circuit output 10.15.20... N07 circuit 13.1
9... Memory circuit for calculation conditions 16... Output of N07 circuit Patent applicant Tokyo Shibaura Electric Co., Ltd.

Claims (5)

[Claims] (1) In a tag selection circuit configured so that multiple taps are not selected simultaneously, an output is derived only when one desired tag is selected, and when multiple tags are selected simultaneously, the A tap selection circuit characterized in that outputs from a plurality of selected tags are disabled and a response equivalent to that when a preset desired tap is selected is performed. (2) A patent characterized in that when a plurality of taps are selected at the same time, the tag selection circuit responds in accordance with the storage conditions of the circuit that stores the conditions before the plurality of taps were selected. A tap selection circuit according to claim 1. (3) If all the taps including the desired tap are not reversed, a response equivalent to selecting a preset tap is performed. tag selection circuit. (4) If all taps including a desired tap are not selected, the tag selection circuit responds in accordance with the memory conditions of the circuit that stores the tap conditions before a tag is no longer selected. The tap selection circuit according to claim 1 (5) If multiple taps are selected at the same time, or if all f is not selected, an alarm is issued after a certain period of time. The tap selection circuit described in Section 4.