JPS5819132B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

For example, as a wiring structure of a semiconductor integrated circuit IC, the first
There are things like those shown in Figures a) and b.

In the figure, a diffusion layer 2 serving as a first wiring layer is formed on the surface of a semiconductor substrate 1, and a second layer is formed through this diffusion layer 2 and an insulating film 3 formed on the surface of the semiconductor substrate 1. An aluminum film 4 serving as a wiring layer is formed to intersect with the diffusion layer 2.

A two-layer wiring with such a configuration has a second wiring layer +
Since a certain aluminum film 4 can be formed on a flat insulating film 3 surface, it is known as a highly reliable film with no step breaks.

However, in an integrated circuit incorporating a silicon gate MOS transistor in which a source layer and a drain layer are formed in a self-aligned manner using a gate electrode as a mask, the gate electrode is extended as it is as a wiring layer, and this wiring layer is used as a second layer. It is not possible to manufacture the above structure in which the wiring layer is used.

This was an impediment to improving the degree of integration.

That is, as shown in the second figure, on one side of the semiconductor substrate,
In parallel with the manufacture of silicon gate MOS transistors,
An oxide film 3a is formed simultaneously with the gate oxide film, and a polycrystalline silicon layer 5, which is a second wiring layer, is formed simultaneously with the gate electrode.

Then, at the same time as the source layer and the drain layer, a diffusion layer 2, which becomes the first wiring layer, is formed, but the polycrystalline silicon layer 5 is used as a mask for the portions that intersect with the polycrystalline silicon layer 5, which is the second wiring layer. As a result, a diffusion layer is not formed, resulting in a disconnection state.

1 Therefore, the purpose of the present invention is to use the gate electrode as a mask,
In a method for manufacturing a semiconductor device incorporating an MIS type semiconductor element by forming a source layer and a drain layer in a self-aligned manner,
The present invention provides a method for manufacturing a thin semiconductor device in which a diffusion layer is a first wiring layer, and a layer formed simultaneously with the gate electrode is a second wiring layer i.

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 3 is a configuration diagram showing an embodiment of a semiconductor device manufactured according to the present invention.

In the figure, a diffusion layer of a conductivity type different from that of the semiconductor substrate 11 is selectively formed on the main surface of a single semiconductor substrate 11.

This diffusion layer constitutes a source layer 12, a drain layer 13, and a first wiring layer 14 connected to the drain layer 13 of the silicon gate MOS transistor.

A diffusion layer is not connected to a portion of the first wiring layer 14 that intersects with a second wiring layer to be described later, and ions of the same conductivity type as the diffusion layer are selectively doped into the semiconductor substrate 11. They are connected by an implant layer 15.

The source layer 12. A gate oxide film 16 is formed on the semiconductor substrate 11 between the drain layers 13 and slightly extends to each layer.
is formed, and a gate electrode 17 made of a polycrystalline silicon layer is formed on this gate oxide film 16.

This gate electrode 17 is extended as it is to become a second wiring layer 18, and this second wiring layer 18 has a gate oxide film 18, especially in a portion where it intersects with the first wiring layer 14.
It is insulated from the first wiring layer 14 by an oxide film 19 formed at the same time as 6.

A relatively large field oxide film 20 having a thickness of one layer is formed in a region on the semiconductor substrate 11 excluding the region where the transistor A and the first wiring layer 14 are formed. .

Further, an oxide film 21 is formed over the entire main surface of the semiconductor substrate 11 processed in this way.

This oxide film 21 is provided with a contact hole that exposes a part of the source layer 12, and a wiring layer 22 that is connected to the source layer 12 at this contact hole is formed on the surface of the oxide film 21.

An embodiment of the method for manufacturing a semiconductor device configured as described above will be described below in sequence with reference to FIGS. 4a to 4e.

FIG. 4a: The main surface of the semiconductor substrate 11 is heat treated in an oxidizing atmosphere to form an oxide film 20 thereon.

Then, the oxide film 20 corresponding to the region where the silicon gate MOS transistor A and the first wiring layer 14 are to be formed is selectively etched to expose a part of the semiconductor substrate 11.

Then, by heat-treating the exposed surface of the semiconductor substrate 11 in an oxidizing atmosphere, a thin oxide film 23 is formed thereon.
form.

FIG. 4b: A photoresist film 24 is formed on the entire surface of the oxide films 20 and 23, and a portion of the photoresist film 24 corresponding to the intersection of the first and second wiring layers to be formed in a later process is removed. Remove by photo etching.

Then, using the remaining photoresist film 24 as a mask,
An ion implantation layer 15 is formed on the surface of the semiconductor substrate 11 by doping an impurity of a conductivity type different from that of the semiconductor substrate 11 using an ion implantation method.

FIG. 4C: After the photoresist film 24 is completely removed, a polycrystalline silicon layer is formed on the entire surface of the oxide films 20 and 23. FIG.

Then, by selectively etching this polycrystalline silicon layer appropriately, a gate electrode 17 of a silicon gate MOS transistor and a second wiring layer 18 are formed.

4th d: Gate electrode 17. The exposed oxide film 23 is removed using the second wiring layer 18 and field oxide film 20 as a mask.

As a result, the remaining oxide film 23 under the gate electrode 17 becomes the gate oxide film 16, and the oxide film 23 under the second wiring layer 18 becomes the second wiring layer 18 and the first layer formed in a later process. This becomes an insulating film 19 that insulates the wiring layer.

Then, by diffusing impurities of a conductivity type different from that of the semiconductor substrate 11 into the exposed surface of the semiconductor substrate 11, the source layer 12. A drain layer 13 and a second wiring layer 18 connected to the drain layer 13 are formed.

In this case, a diffusion layer is not formed in the portion intersecting with the second wiring layer 18, but it is electrically connected by the ion implantation layer 15 formed in advance.

FIG. 4e: For example, CVD (Chemical Vapo) is applied to the entire surface of the semiconductor substrate 11 processed in this way.
An oxide film 21 is formed by a ur deposition method or the like, and a hole for exposing a part of the source layer 12 is formed by a selective etching method.

Then, an aluminum layer is formed on the entire surface of the oxide film 21 including the holes, and a wiring layer 22 connected to the source layer 12 is formed by a one-selective etching method.

In this way, even if the second wiring layer is formed in parallel with the silicon gate MOS transistor at the same time as the gate electrode, and the first wiring layer is formed using a diffusion layer at the same time as the source/drain layer, the first wiring layer Since an ion implantation layer is previously formed at the intersection of the second wiring layer, the diffusion layer is electrically connected and will not be disconnected as in the conventional case.

That is, even if the lowest voltage (generally the substrate potential) during circuit operation is applied to the first wiring layer, the ion implantation layer is in a sufficient depletion mode and a conduction channel is generated.

Note that when an N-channel MOS transistor with a power supply voltage of 5V is incorporated into the wiring structure described above, the maximum voltage applied to the first wiring layer is 5V, and the lowest voltage applied to the gate electrode of the MOS transistor is It has the same OV as the board.

Therefore, the voltage between the source layer and substrate is 5V, and the voltage between the gate and substrate is 5V.
With the source-to-source voltage at -5V, the first wiring layer needs to be in a conductive state at the intersection with the second wiring layer.

That is, the threshold voltage must be lower than -5V, but assuming that the substrate bias constant is 0.6JV,
From this relationship, it is sufficient to set the voltage to -6V or less.

This example describes a two-layer wiring structure in which a silicon gate MOS transistor is incorporated, and the source layer and
Other MOS transistors forming the drain layer may also be used, such as a molybdenum gate MO8 transistor or a tungsten gate transistor.

Moreover, it goes without saying that the device is not limited to a MOS transistor, but may also be an MIS type element.

As described above, according to the method for manufacturing a semiconductor device according to the present invention, a diffusion layer is formed in a semiconductor device incorporating an MIS type semiconductor element in which a source layer and a drain layer are formed in a self-aligned manner using a gate electrode as a mask. The first wiring layer and the layer formed simultaneously with the gate electrode can be used as the second wiring layer.

[Brief explanation of drawings]

FIGS. 1a and 1b are diagrams illustrating an example of a conventional semiconductor device,
FIGS. 2a and 2b are diagrams for guiding the present invention, FIG. 3 is a configuration diagram showing an example of a semiconductor device manufactured according to the present invention, and FIGS. 4a to 4e are diagrams showing a method for manufacturing a semiconductor device according to the present invention. It is a process diagram showing one example. 1.11...Semiconductor substrate, 2...Diffusion layer, 3...Insulating layer, 4...Aluminum film, 5...Many Crystalline silicon layer, 12...
...Source layer, 13...Drain layer, 14...
...First wiring layer, 15...Ion implantation layer, 16...Gate oxide film, 17...
...Gate electrode, 18...Second wiring layer, 1
9,21゜23... Oxide film, 20...
Field oxide film, 22... Wiring layer, 24...
...Photoresist film.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor device incorporating an MIS transistor by forming a source layer and a drain layer in a self-aligned manner using a gate electrode as a mask, an insulating film to be a gate insulating film and a wiring intersection insulating film is formed on a semiconductor substrate. forming a defect doped layer by implanting ions through the insulating film into the semiconductor substrate under the insulating film that will become the wiring intersection insulating film; and forming a defect doped layer on the insulating film. a step of simultaneously forming a wiring layer; and a step of simultaneously forming a source layer, a drain layer, and a second wiring layer by diffusing impurities into the semiconductor substrate using the gate electrode and the first wiring layer as a mask; A method for manufacturing a semiconductor device, comprising forming a second wiring layer connected by an impurity-doped layer under an intersection insulating film and insulated from a first wiring layer via the insulating film.