JPS58190161A - Secondary scanner - Google Patents

Abstract

PURPOSE:To prevent the generation of the feed unevenness due to a transient change of speed at the stopping of secondary scanning and restarting, by adding a starting timing pulse generating circuit and then discontinuing the secondary scanning when the data bits are redued down to that of <=1 scanning line. CONSTITUTION:A storing circuit 1 stores picture elements equivalent to plural scanning lines to write and read successively the data bit groups. A phase signal generating part 2 produces a phase pulse signal with a prescribed cycle and prior to a data column. A storage quantity detecting circuit 3 is produced at the lower limit value equivalent to the sum of a prescribed number of scanning lines and ''1'', then generates a storage quantity display signal which disappears at the upper limit value equivalent to the difference between the total storage quantity and a prescribed number of scanning lines. A start timing pulse generator 4 counts and stores the time difference of generation between a phase pulse signal obtained after generation of the storage quantity display signal and a motor clock and then produces a start timing pulse after the storage quantity display signal is estinguished.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sub-scanning device, and more particularly to a sub-scanning device in a line-scanning recording device that records and reproduces image information obtained from compressed encoded information.

Description of Prior Art Image information consisting of a series of data bit groups having a data beat sequence for each scanning line of a binary signal is sequentially written into a storage circuit having a total storage capacity tt for storing t% of pixels for a plurality of scanning lines. There is a line-scanning type recording device 1 that sequentially reads out and records/reproduces a series of data bits in response to a data bit group ta output instruction signal.

In this recording device, by stopping and starting sub-scanning according to the storage amount of data bits stored in the storage amount M, data bits stored in the storage circuit that occur due to changes in the compression ratio are This prevents the remaining amount from reaching 4.

- When the remaining heat of the tabinode becomes less than 111 scans, reading of the memory circuit is stopped and sub-scanning is temporarily stopped, and the data bit written in the memory circuit is equal to or less than 111 scan lines. When the amount of memory remaining for the main purpose is reached, start-up and sub-scanning are started again.

In this way, when stopping and restarting scanning, the regeneration power distribution 11
lVs, the interval between the scanning line at the time of start-up and the previous scanning line differs from the interval between scanning lines when sub-scanning is performed continuously.

Therefore, a step motor with good responsiveness during stopping and starting is used for driving the sub-scanning, but transient speed fluctuations during stopping and starting are unavoidable due to the inertial force of the sub-scanning mechanism.

Disadvantages of conventional mosquito retardation Due to this speed change, the above-mentioned scanning interval fluctuates, causing uneven feeding and deteriorating recorded image quality. There is a drawback that uneven feeding occurs due to fluctuations.

OBJECTS OF THE INVENTION An object of the present invention is to provide a sub-scanning device that can prevent noise caused by uneven feeding due to the transient speed K11Ell+ when stopping and restarting sub-scanning.

Configuration of the Present Invention The sub-scanning device of the present invention includes a series of data bits t1-, which are composed of a data bit string of a binary signal corresponding to each pixel.
One memory circuit with a total storage capacity for storing pixels for a plurality of scanning lines, which sequentially reads out the series of data bits l# in response to an oath and continuous output instruction (No. 71), and the data bit string. a phase 1d generation unit that generates a phase pulse signal having a predetermined cycle and preceding each of them; and a record 11111i of the series of data bits stored in the storage circuit
Generating a storage amount display signal that occurs when il reaches a lower limit corresponding to the sum of a predetermined number of feet and l, and disappears at an upper limit corresponding to the difference between the total storage capacity and the predetermined number of device sets. a storage amount detection (b) path that counts and stores the time difference between the generation of the phase pulse signal after the storage amount display signal is generated and a motor clock subsequent to the cough phase pulse signal, and the storage amount display signal disappears; a startup timing pulse generation circuit that generates a startup timing pulse after the time difference elapses after the supply of the phase pulse signal following the generation of the storage amount display signal; It occurs after a predetermined period of time has elapsed after extinction and disappears again after the predetermined number of scanning phases has been scanned.iI! The motor clock generation instruction signal is generated in response to the generation of the start timing pulse, and the I9r'? signal is generated after the predetermined time has elapsed. l A start/stop control circuit that generates a reversal instruction signal sound that disappears after several scan lines have been scanned; a counter circuit that generates the motor clock in response to the motor clock generation instruction signal; and a sub-scan control circuit that generates the motor clock in response to the motor clock generation instruction signal. Driving step 7: a rigid scanning motor IIA driving circuit for driving motor 'fr and reversing the step motor in response to the reversal instruction signal, and a circuit for scanning the predetermined number of scanning lines after generation of the storage amount display signal. and a read instruction signal generation circuit that generates the successive instruction signal that disappears after scanning the predetermined number of scanning lines after the disappearance of the storage amount display signal. Examples will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The sub-scanning device shown in FIG. Memory amount detection circuit 3. Start-up timing pulse generation circuit 4. Start/stop control circuit 5. ll! l Loss output signal generation circuit 6. Counter circuit 7. It is composed of a sub-scanning motor control unit 8 and a step motor 9t.

Below, the operation of the sub-scanning device shown in FIG. 1 will be explained in detail with reference to FIGS. Block diagram @3 is a detailed block diagram of the start/stop control circuit in the embodiment shown in FIG. 1, FIG. 4 is a detailed IPF block diagram of the successive instruction signal generation circuit in the embodiment shown in FIG. 1, and FIG. is a time chart for explaining the operation of the start-up tying pulse generation circuit shown in Fig. 2, and Fig. 6 is a time chart for explaining the operation 1r of the embodiment shown in Fig. 1. ○ One point in Fig. 1 A silver halide recording medium such as a film or photographic paper is attached to the outer periphery of a recording cylinder 21 of a recording scanning section 20, which is shown surrounded by a chain line. The recording cylinder 21 is rotated by a main scanning motor 22, and the main scanning motor 22 has a synchronization clock generation time of %11.
The drive power from the main scanning motor unit side circuit 12, which is controlled by the synchronization signal S2 from the main scanning motor circuit 12, performs synchronization [g1].

A phase signal generating section 2 is solidly layered on the rotating axis (b) of the recording cylinder 21, and a phase pulse signal B is generated every time the recording cylinder 21 rotates.

Recording light #25 flashed by the output signal from recording time mlO
The moving table 25 on which the food is placed fills the recording circle by the rotation of the feed screw 23 which is rotated by the step motor 9 for one-stroke feeding.
The axis of rotation moves in one direction.

Operation at startup When the recording device is initially started, the storage circuit l in the sub-scanning device has a total storage capacity M (capable of storing data bit strings for M scanning lines) and a predetermined number N of scanning lines (capable of storing data bit strings for M scanning lines). corresponds to the number of data bit strings Imi′lL and the number of scanning lines N
is the time from time to to time t! shown in FIG. Up to this point, the storage amount display signal A from the storage amount detection cycle [3] is 10-'', and as shown in Figure #I6, the step motor 9 is stopped because the motor clock n[ has not been generated. Further, the continuation instruction signal G becomes "high" and stops instructing the p1 storage circuit 1 to read.

The storage circuit 1 stores a series of data bit groups consisting of binarized signals corresponding to each Ij7iJ accumulation to the synchronous clock generation circuit 1.
A write address is generated as a clock pulse 51tl-pk from 1 and sequentially written.

In FIG. 1, the memory amount detection circuit 3 constantly detects the difference between the convolution address and the read address caused by the four-pulse 81 generated in the memory circuit l, and the difference is (M-
N) When the number of data bits corresponds to the number of scanning lines for main purpose, at time 11 shown in FIG. In the start-up timing pulse generation circuit 4, at time t2 shown in FIG.
1 is written as t'l1it when the output signal a becomes high at the next phase pulse signal Bl after the display signal A becomes high.
The signal e is supplied to the No. 16 afd flip-flop 42 and the No. 7 lip-flop 45, and the signal e from the flip-flop No.
- Low” is output. 7 The signal from Ritz Frog 42 is 1 high because motor clock E is not generated.
maintain the condition.

The exclusive-reason circuit 43 is supplied with the signal a and the signal 7''.
L exclusive sum is taken, and the NAND product of the resulting 1-LOW output signal and the signal S is taken by the NAND circuit 44,
Negative product same! The signal d is output from 44 as "high".

Next, the negative product of the signal e of ``10-'' and the signal d of [-high J is taken by the negative product circuit 46, and the resulting signal ``10-'' and the signal d of the up-down counter 48 are The "high" activation timing pulse C is supplied to the NAND circuit 47, the NAND product is taken, and the signal 1 is output as "Low".

Here, at initial startup, the up/down counter 48 is set to the initial value, and when the signal l is supplied from the negative product circuit 47 at "low", the up/down counter 48 enters the down mode and zero is detected. A "low" activation timing pulse C is generated.

The activation timing pulse C is supplied to the negative product circuit 47,
The non-additive product with the other input signal ``1 high'' is taken, and the signal i is converted to ``high''. signal! The up/down counter 48 is set to the initial value by converting the flag to "1 high".

On the other hand, the start timing pulse C is the start/stop control time II?
;5 is supplied. In the start/stop control circuit 5 shown in FIG. 3, the start timing pulse C is supplied to an exclusive negative OR circuit 59. The taunter 51 is in an operating state when the output signal of the exclusive negative OR circuit 52 is "low", but the storage amount display signal A of one input of the exclusive negative OR circuit 52 is
is "high" and the output signal of the other input 7 lip-flop 55 is "I", so the output signal of the exclusive negative OR circuit 52 is "high" and the counter 51 does not operate.

Therefore, the output signal of Karan 451 is [high],
The signal k is inverted to 10-'' by the inverting circuit 57 and the delay circuit 58
The signal p, which is the other input of the exclusive negative OR circuit 59 delayed by a predetermined time, is 10-''. Therefore, the output signal of the exclusive negative OR circuit 59 becomes high, and the motor clock generation instruction signal from the Frison 70 knob 60 becomes 10.
-” is output.

Next, in FIG. 1, motor clock generation instruction signal I
J is supplied to the counter circuit 7. The motor clock E is set in the counter in advance with a clock pulse S corresponding to the period of the motor clock frequency corresponding to the sub-scanning speed, and the counter is activated when the motor clock generation instruction No. 1d becomes "low". The periodic pulse generated by starting counting of clock pulses Sl and repeating the counting every time it reaches a set value is obtained by dividing the frequency of the periodic pulse by V2.

When the rIMj scan motor drive circuit 8 is supplied with the motor clock E, it supplies -motive force to the step motor 49 to start sub-scanning. The above is the operation at the time of initial startup at time t2 shown in FIG.

Start of reading In FIG. Counter 64. Equipped with a tongue foot product circuit 651, an inverting circuit 66, a slip 70, and a tab 67, the phase pulse signal Bt- is counted from the phase pulse signal H1 after the storage amount display signal A becomes "high" and a reading instruction is given to the (Nil) side. When the signal G is set to 10-'' and the signal k supplied from the start/stop control circuit 5 becomes 10-'', the continuous instruction signal G1
Set to ``rl high''.

That is, at time t1 shown in FIG.
When the display signal A becomes "High", as shown in Fig. 4,
Since both of the two inputs of the NAND circuit 65 become "no screen", the output becomes "10-" and the counter 64 becomes operational.

The counter 64Vi is preset to 0+1) by the preset switch 63, and the phase pulse signal B is changed from the phase pulse signal Bl at time t2 to (N+1) at time t3.
When the phase pulses are counted up to N+1, zero is detected and a 10-'' pulse signal is output, and the sonohals signal is passed to the inverting circuit 66 as a ``high'' pulse 0! The signal is converted into a signal and supplied to a flip-flop 67.

Therefore, the read instruction signal q of the output of the flip-flop 67
is converted to 10-''. When the read instruction signal q becomes 10-'', the output of the NAND circuit 65 changes to ``A'', and the counter 6
4 is set as the initial value.

In FIG. 1, when a "low" continuation instruction signal q is supplied to the memory (b) circuit l, the memory circuit l sequentially reads out the stored data bits at the continuation address generated as the clock pulse Stt clock and records the data bits. The signal is supplied to the circuit IO, and recording and reproduction of image information is started in the recording and scanning section 20.

The temporary stop encoding compression rate of sub-scanning and reading decreases, the start-up speed becomes faster than the writing speed, and the data bits stored in the storage circuit 1 gradually decrease, causing the storage amount detection circuit 3 to decrease. The number of scanning lines (Ni
1) When it is detected that the amount corresponds to the duty, the 6th
At time t4 shown in the figure, the storage amount display signal PER is converted to [-LOW].

Next, the activation timing pulse generation circuit 4 is connected to the clips 70, 41, 42 and 45, as shown in FIG. Exclusive logical cleverness 1 @43. NAND circuit 44.46 and 4
7 and an up/down counter 48, it counts and holds the time difference X between the phase pulse signal average and the subsequent motor clock E after the storage amount display signal A reaches 10-'', and the storage amount display signal A reaches 10-''. A start-up tie ink pulse Cft is generated after the time difference X has elapsed from the phase pulse signal Bl after it becomes "high".

That is, as shown in Fig. 85, when the memory capacity indication Oh becomes "-" at one hour t4,
When the phase pulse signal S is supplied at 5, the 1g signal a is output from the 7 logic flop 41 at 10-'', and the up/down counter 48 enters the up mode operating state and starts counting clock pulses S,.

At the same time, the exclusive OR circuit 43 outputs "low" signals - and 1.
The exclusive OR of the output signal ``high'' and the output signal ``high'' is taken, and the negation of the output signal ``high'' and the signal ``s'' is performed in the NAND circuit 44, and the signal d is On the other hand, when the input of the clip 70k 42 becomes 10-'', the output signal is converted to 10-'' at time t6 shown in FIG. 85 at the rise of the motor clock E. Since the clock input is [-low], the 7-rig clock float 45 does not operate.

Next, at time t6, the exclusive OR circuit 43 calculates the exclusive OR of the low signal a and the low signal The output signal and the signal d are NANDed by the NAND circuit 45, and the signal d is
converted to "high".

When gK No. d becomes "high", 7 horn down counter 48
stops counting, and the counting result is held in the up/down counter 48. By the above operation, from time ts to time t
The time difference X up to 6 is retained.

Here, the operations from time ts to time t· in FIG. 5 correspond to the times shown in FIG. 6 with the same symbols. In addition, startup tie i
The generation operation of the ng pulse C will be described later.

Next, as shown in FIG. 3, the start/stop control circuit 5 is activated by a preset switch 50. Counter 51. exclusive logical yield lol
652 and 59.71Jg 70g 53.55.5
8 and 60. Up/down counter 54. Delay circuit 5
61 inversion circuit 57 is further provided with an AND circuit 61 and generates a motor clock generation instruction signal and an inversion instruction signal F sound.

When the storage amount display signal A becomes "low" at time t4 shown in FIG. 6, the exclusive negative OR circuit 5
Since the signal from the 7 rig 70 tube 55, which is the other input of 2, is "high", the output signal of the exclusive negative OR circuit 52 becomes "low" and becomes operational, and the preset switch 50 causes ( N+1) is set.

Next, the phase pulse signal Bt- is counted from the phase pulse signal B1 at time t5, and the phase pulse signal "N+1" of the sieve is counted. At time t7 shown in FIG. 6, zero is detected and the signal Output k at 10-'' On the other hand, at the time tsVC when the phase pulse signal H1 is supplied after the one-way proof storage display signal A becomes “low”, 7”70
At time t7 when the output signal of the toggle 53 becomes "low" and the up/down counter 54 enters the up mode operating state and starts counting the motor clock E from the motor clock E1, the 0 signal k becomes "10-". The logical product of the signal and the output signal m of the up/down counter 54 is taken by the logical product circuit 61, and the result is 10-
" output signal is supplied to the reset terminal of the flip-flop 60 and the flip-flop 60 is reset, so the output motor clock generation instruction signal -kjD is converted to "no-i". Next, in FIG. , when the motor clock generation instruction multiplication gl) reaches 1 no.i, the counting of clock pulses 81 in the counter circuit 7 stops when the next motor clock E is generated, the step motor 4I9 stops, and the sub-scanning is interrupted. Ru. At the same time, the up/down counter 54 holds the counting results of the motor clock E from the motor clock El to the motor clock E. Here, the number nF'i of the retained mo-clocks E is a value corresponding to the number of scanning lines of the book.

On the other hand, in the successive instruction signal generation circuit 6 shown in FIG.
At time t7 shown in FIG. 6, the flip 70 knob 67 is reset and the output continuation instruction signal q is converted to "high", and the readout of the memory circuit l becomes the storage amount display signal. After the 10th issue of the book (N+1), the scanning of the wood grain is stopped from the start, and the recording and reproduction in the recording scanning section 20 is interrupted.

Furthermore, in FIG. 3, the signal p is converted into a "low" signal by the μ inversion circuit 57 and is continuously burned for a predetermined period of time.
Therefore, at time ta shown in FIG. 6, the exclusive negative OR circuit 59vc is supplied. Just set the time to stop.

When the sub-scanning return operation is exclusive jA, the logic circuit 59 outputs the signal p of "No."
Exclusive negative OR with "high" startup timing pulse C?
The resulting "high" output signal is supplied to the clock terminal of the 7-rig float 160, and the 7-rig 770 knob 60 outputs a "low" motor clock generation instruction signal.

Motor crotch generation instruction signal 1' o -J to G
Ref exchange! The counter circuit 7 shown in FIG. 1 starts generating the motor clock E.

At the same time, the "high" output signal p from the delay circuit 56 is
When the clock signal is supplied to the flip-flop 58, the flip-flop 58 outputs an inversion instruction signal F at "low" level. In FIG. 1, a reversal instruction signal P' is supplied to a sub-scanning motor drive circuit 8 to reverse the rotational direction of a step motor 9. Therefore, the step motor 9 rotates in the reverse direction.

The above is the operation based on the time shown in FIG. 6, and the movable platform of the ninth sub-scanning in which the step motor 419 is reversed is J! Start moving in the opposite direction.

On the other hand, in FIG. 3, when the inversion instruction signal F is output from the 7 rig 70 knob 58 at "low", the up/down counter 454 enters the down mode and counts down the held counting result using the motor clock E as a clock. , zero is detected at the time shown in FIG. 6 counted from motor clock El to motor clock UG, and a "low" pulse signal m is output.

(The low signal m is logically ANDed with the high signal in the logical product circuit w161, and the output “low” signal is 7
It is supplied to the reset m terminal of the lip lock 6o, and the motor clock generation instruction signal output from the 7 lip 70 knob 60 changes to "high", the generation of the motor clock E from the counter circuit 7 is stopped, and the step motor 4I9 is stopped. do.

At the same time, the signal m of "10-" is supplied to the reset 4 children of the 7-lip 70-tube 58, and the inversion instruction signal F output from the 7-lip 770-tube 58 becomes ")・i", and the up/down counter 54 Set to initial value. Further, as the reversal instruction signal F changes to "NO", the rotational direction control of the step motor 9 in the sub-scanning motor drive circuit 8 returns to the steady state.

The above is the operation from time ta to time t9 shown in FIG. 6, and the sub-scanning movable table 24 is accurately returned to the predetermined number of scanning lines.

Resumption of sub-scanning and reading In FIG. 1, the writing of data bits to the memory circuit l progresses and the storage capacity reaches a state where the number of data bits corresponding to the main duty is left on the scanning line for the total size fM. At times t and O shown in the figure, the storage amount detection circuit 3 detects this and converts the storage amount display signal A to 1 high.

・In FIG. 2, the activation timing pulse generation circuit 4 generates 7 at the rising edge of the phase pulse signal B at time t11 shown in FIG.
The output signal a of the lip 70 and the tug 41 becomes [high], and the 70
At time tll when the output signal e of the lip 7a block 45 becomes 10-'', the output signal bil of the lip flop 42 is low, and the exclusive OR of the signal a and the signal 43 is the exclusive OR circuit 43. The negative product of the resulting "high" signal and the signal d is taken by the NAND circuit 44, and the signal d is output as 171i.

Next, the negative product of the signal e of 10-'' and the signal d of 1 high is taken by the negative product circuit 46, and the resulting bias of ``high'' is -
The negation of wjh and the activation timing pulse C of 1 high of the up-down counter 48 is taken by the negation product circuit 47, and the resulting signal l of 10-'' is supplied to the up-down counter 48, and the amplifier down counter 48 4148 goes into down mode.

The ARABUTA run counter 48 counts the held count results described above using the clock pulse S1, and at the time ttz shown in FIG. The start-up timing of "low" is taken by the constant product circuit 47, the signal l is converted to "high", and the up/down counter 48 is set to the initial value.

As described above, in the operation from time tlG to time text shown in FIG. 5, the time difference from 1 hour 111 to time t12 is equal to the time difference XK from time t6 to time t6.

Further, time tto to time tIZ correspond to times with the same symbols shown in FIG. 6, respectively.

In Fig. 3, the starting timing pulse C of 1゛low''
The signal p of 10-'' is supplied to the μ exclusive negative sum circuit 59.
The resulting 1 high output signal is supplied to the clock terminal of the 7 lip flop 60, and the motor clock generation instruction signal from the 7 lip flop 60 is converted to a low level. Ru. Therefore, the counter unit 7 shown in FIG. 1 generates the motor clock E, the step motor 9 is activated, and the sub-scanning is restarted at time t12 shown in the sixth factor.

Due to the operation from time 110 to time t12, the step motor 49 is started at time 112 under the same conditions as time t when stopped. In addition, in the wJ3 diagram, the start timing pulse C of [-low] is the flip 70. Supply to reset 4 children of knob 55, flip-flop 5
The output signal of 5 becomes "high", and the exclusive negative OR circuit 5
The memory of "high at 2" is subjected to an exclusive negative OR with the display signal A, and the resulting output signal of "/)i" is sent to the counter 51.
is supplied to the counter 51, and the counter 51 is set to an initial value.

Next, in FIG. 4, the successive instruction signal generation circuit 6
At time tlo shown in the figure, the storage amount display signal A is "...
When the signal becomes "A", the successive instruction signal Q is "1 No.", so the NAND circuit 65 calculates the NAND, and the NAND circuit 65 outputs a "Low" signal. Therefore, the counter 64 becomes operational and (N+ 1 ) is set from the preset switch 63. The counter 64 outputs a pulse signal indicating that the storage amount display signal A has been converted into "No Tsutai" and the number "0 is detected when counting 10-". The pulse signal is converted into a "no-i" pulse by the inverting circuit 66 and is supplied to the clock terminal of the frisogefrog 67.

Therefore, the successive instruction signal q from the Frisogefrog 67 is "
The above is the operation at time 11= shown in FIG. resume. As a result, start-up from the start point of the scanning proboscis, which stopped reading out at time 17, can be resumed at time 11m. Recording and reproduction to the medium is performed.

Effects of the present invention As described above, the rigid scanning device i1. of the present invention. A startup timing pulse generation (b) path is added to the memory (b) path, and when the data bits stored in the memory (b) path become less than one scanning line, sub-scanning is stopped and rigid scanning is performed for a predetermined number of scanning lines. When the amount of memory in the memory circuit becomes the difference between the amount of memory stored in the memory circuit and the amount equivalent to the number of required scanning lines, the sub-scanning is stopped and restarted by restarting the sub-scanning at the same timing as when it was stopped. This has the effect of improving the recorded image quality since it is possible to prevent the occurrence of uneven feeding due to transient speed fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 2 is a detailed block diagram of the start-up tying pulse generation circuit in the embodiment shown in FIG. 1, FIG. 3 is a detailed block diagram of the start-stop control circuit in the embodiment shown in FIG. FIG. 6 is a detailed block diagram of the read instruction signal generation circuit in the embodiment shown in FIG. It is a time chart for explaining the operation. In the figure, l...memory circuit, 2...phase pulse signal generation unit, 3...memory amount detection circuit, 4...starting timer...sequential instruction signal generation circuit, 7...counter Circuit, 8... Sub-scanning motor drive circuit, 9... Step motor, A... Notation, it display signal, B... Phase pulse signal, C.../1 Start timing pulse, D. ...Motor clock generation instruction signal, E...Motor clock, F...Inversion instruction signal, q...Continuation instruction signal. Figure 2 Figure 3 <oOooLL, lLl-C

Claims (1)

[Claims] A total memory for storing a plurality of scanning sub-pixels for sequentially writing a series of data bit groups consisting of a data bit string of a binary signal corresponding to each pixel and sequentially reading out the series of data bit groups in response to a read instruction signal. a storage circuit having a capacity; a phase signal generation section that generates a phase pulse signal r preceding each of the data bit strings and having a predetermined period; and a storage capacity of the series of data bit groups stored in the storage circuit. A memory that generates a storage amount display signal that occurs when a lower limit corresponding to the sum of a predetermined number of scanning lines and 1 is reached, but disappears at an upper limit corresponding to the difference between the total storage capacity and the predetermined number of scanning lines. a quantity detection circuit that counts and stores the time difference between the phase pulse signal and the motor clock pulse signal subsequent to the phase pulse signal after generation of the cough memory indicating signal; a startup timing pulse generation circuit that generates a startup timing pulse after the time difference elapses after the pulse signal is supplied; and a startup timing pulse generation circuit that generates a startup timing pulse after the time difference elapses after the pulse signal is supplied; A motor clock generation instruction signal that is generated later and disappears again after the predetermined number of scanning lines have been scanned, and is generated in response to the generation of the activation timing pulse; A start/stop control cycle for generating a reversal instruction signal that causes the blue kvc to disappear; a counter cycle for generating the motor clock in response to the motor clock generation instruction signal; and a fine scan drive step in response to the motor clock. sub-scanning motor drive repair for driving a motor and reversing the step motor in response to the reversal instruction signal;
generating the read instruction signal which disappears after scanning the predetermined number of scanning lines after the occurrence of the memory award display signal and which temporarily occurs while scanning the predetermined number of scanning lines after the memory type display signal disappears; A sub-scanning device 1n characterized in that it includes a successive instruction signal generation circuit.